Retinal Prosthesis Dissertation - Student Home Pages

3.6 AER concept in context ............................................................................................................... 66
3.7 AER data format .......................................................................................................................... 67
3.8 Behavioural test image to be used .............................................................................................. 71
3.8.1 Other test images ................................................................................................................. 74
3.9 Biphasic pulse ............................................................................................................................. 74
3.10 Concluding this chapter ............................................................................................................. 76
Chapter 4 Sender chip ......................................................................................................................... 79
4.1 Sender concepts ......................................................................................................................... 80
4.2 Sender AER format ..................................................................................................................... 85
4.2.1 Alternative (discounted) sender AER format ........................................................................ 86
4.3 Test setup ................................................................................................................................... 87
4.4 Sender chip reports ..................................................................................................................... 87
4.4.1 Power Analysis .................................................................................................................... 88
4.5 Sender schematic ........................................................................................................................ 88
4.6 Chapter summary ........................................................................................................................ 91
Chapter 5 Receiver chip ...................................................................................................................... 94
5.1 Clocking calculations (sender) ..................................................................................................... 94
5.2 Power Analysis ....................................................................................................................... 96
5.3 Receiver schematics ................................................................................................................... 97
5.4 Clocking calculations (receiver) ................................................................................................... 99
5.5 Programming components descriptions ...................................................................................... 99
5.5.1 Incoming (short) AER stream ............................................................................................. 100
5.5.2 Production of colour data streams ..................................................................................... 100
5.5.3 Convert to long format........................................................................................................ 100
5.5.4 Production of output streams ............................................................................................. 100
5.6 Summary of FPGA resource utilisation...................................................................................... 101
5.7 Post processing for electrodes .................................................................................................. 101
5.8 Stimulator Retinal Interface ....................................................................................................... 103
5.8.1 Factors affecting current requirement for stimulation ......................................................... 103
5.8.2 Electrode size and positioning in current retinal approaches ............................................. 104
5.8.3 Recent developments ........................................................................................................ 104
Chapter 6 Concluding chapter.......................................................................................................... 105
6.1 Conclusions and results ............................................................................................................ 105
6.2 Implementation of design .......................................................................................................... 106
6.2.1 DAC operation ................................................................................................................... 107
6.2.2 Envisaged retinal array ...................................................................................................... 110
6.2.3 Connecting the detailed engineering to the overall concept ............................................... 111
6.2.4 Differences between proposed technique and current retinal implants .............................. 112
6.3 Lower power FPGA ................................................................................................................... 113
6.4 AER between sender and receiver chip .................................................................................... 115
6.5 Post Processing Interface ......................................................................................................... 116
6.6 Pre processing .......................................................................................................................... 117
6.7 Future work ............................................................................................................................... 117
6.7.1 Surgical implantation .......................................................................................................... 118
6.7.2 Inductive linking considerations ......................................................................................... 119
6.7.3 Initial configuration ............................................................................................................. 119
Bibliography ....................................................................................................................................... 120
%Appendix A MATLAB ..................................................................................................................... 133
--Appendix B FPGA Test setup......................................................................................................... 142
--Appendix C FPGA Sender chip ...................................................................................................... 150
--Appendix D FPGA Receiver chip ................................................................................................... 154
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