1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
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FEI KEMT<br />
4 Elliptic Curve Method <strong>in</strong> <strong>Hard</strong><strong>ware</strong> 55<br />
4.1 Parameterisation of the ECM Algorithm . . . . . . . . . . . . . . . . 56<br />
4.1.1 Phase 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56<br />
4.1.2 Phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57<br />
4.2 Design of the ECM Unit . . . . . . . . . . . . . . . . . . . . . . . . . 58<br />
4.2.1 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 59<br />
4.2.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . 59<br />
4.2.3 Choice of the Arithmetic Algorithms . . . . . . . . . . . . . . 60<br />
4.2.4 Parallelization of the Algorithm . . . . . . . . . . . . . . . . . 64<br />
4.3 Implementation of the ECM Unit . . . . . . . . . . . . . . . . . . . . 65<br />
4.3.1 <strong>Hard</strong><strong>ware</strong> Platform . . . . . . . . . . . . . . . . . . . . . . . . 65<br />
4.3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66<br />
4.3.3 ECM-Based Acceleration of GNFS: a Case Study . . . . . . . 67<br />
4.4 Conclusions and Future Steps . . . . . . . . . . . . . . . . . . . . . . 69<br />
5 True Random Number Generator - prelim<strong>in</strong>aries 71<br />
5.1 Randomness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71<br />
5.1.1 Def<strong>in</strong>itions of Randomness . . . . . . . . . . . . . . . . . . . . 72<br />
5.1.2 Random Number Generator . . . . . . . . . . . . . . . . . . . 73<br />
5.1.3 Applications of Random Numbers . . . . . . . . . . . . . . . . 75<br />
5.2 TRNG Implementations <strong>in</strong> Digital Systems . . . . . . . . . . . . . . . 76<br />
5.2.1 Sources of Randomness . . . . . . . . . . . . . . . . . . . . . . 77<br />
5.2.2 Survey of Designs Based on Jitter . . . . . . . . . . . . . . . . 82<br />
5.3 PLL-Based TRNG on FPGA . . . . . . . . . . . . . . . . . . . . . . 85<br />
5.3.1 Randomness Extraction Method . . . . . . . . . . . . . . . . . 85<br />
5.3.2 Coherent Sampl<strong>in</strong>g . . . . . . . . . . . . . . . . . . . . . . . . 88<br />
5.4 Test<strong>in</strong>g of TRNGs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89<br />
5.5 Attacks aga<strong>in</strong>st TRNG . . . . . . . . . . . . . . . . . . . . . . . . . . 91<br />
5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92<br />
6 True Random Number Generator 94<br />
6.1 Clock Synthesis <strong>in</strong> FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 94<br />
6.1.1 PLL as Source of Randomness . . . . . . . . . . . . . . . . . . 96<br />
6.2 PLL-Based TRNG on FPGA . . . . . . . . . . . . . . . . . . . . . . 101<br />
6.2.1 PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . 101<br />
6.2.2 Analysis of TRNG <strong>in</strong> Altera Stratix FPGAs . . . . . . . . . . 103<br />
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