1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
q
x
i
S (j)
2 w-1 S (j)
1 w-1
i
Y (j)
w-1 M(j)
w-1
FA FA
FA
S (j-1)
2 w-1
FA
S (j)
2 w-2 S (j)
1 w-2
S (j-1)
1 w-1
S (j-1)
2 w-2
Y (j)
w-2 M(j)
w-2
FA
S (j-1)
1 w-2
. . .
. . .
S (j)
0 S (j)
2 1 0
Y (j)
0
FA
M(j)
0
S (j-1)
0 S (j-1)
2 1 0
Figure 2 – 3 Block diagram of the CSA-based w-bit MWR2MM processing element (CSA PE)
based on FA
of the MWR2MM CSA algorithm. Positive property of the implementation is its
independence on carry chain logic on the target platform.
Carry-Propagate Adder Unit Recent FPGAs contain high-speed interconnect
lines between adjacent logic blocks which have been designed to provide an efficient
carry propagation. The CPA PE architecture presented in this thesis is optimal for
the implementation of the MMM unit on any FPGA that has dedicated carry logic
capability (e.g. modern Altera and Xilinx FPGAs). The basic organization of the
ALU consists of two layers of conventional CPAs as shown in Figure 2 – 4.
Unlike the CSA PE, the CPA PE does not support a feature of arbitrary word
width w. The border for the number of FAs in one row is given by the target
technology. The more LEs are chained by fast (and short) interconnection the higher
the word width can be, achieving comparable speed results to CSA PE. The value
of the carry signal raised in the first FA from the left side (for LSB) is subsequently
processed in the adjacent FA that outputs another carry signal for the third adder
in the row. . . In this way the carry signal is propagated till the most right FA (for
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