1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
7 Research Contribution
With this thesis we contributed to the field of hardware implementation of public-key
cryptographic system elements. We discussed the aspects of algorithm adaptations
and system architectures for modular multiplier and cryptanalytic hardware. Ran-
domness extraction method based on clock circuitry was evaluated and new findings
were presented.
The research contribution were achieved in the following topics:
• Optimised Montgomery modular multiplier implementation in hardware.
• The elliptic curve method implementation in hardware.
• Evaluation of random number generator based on clock circuitry in FPGAs.
Optimised Montgomery modular multiplier implementation in hardware
Two most popular public-key cryptographic algorithms – the RSA and ECC use
extensively modular operations with large numbers. The MM can be a very slow
operation when performed on general-purpose computers, therefore can be acceler-
ated by an effective hardware implementation.
We analysed algorithms for Montgomery MM and architectures for their effec-
tive implementation suitable for reconfigurable hardware structures. Our attention
was paid to keep the scalability and parametrisation of multiplier unit also in the
other parts of the system and find an optimal model for division of computational
load between the software and hardware part of the system. The results of area oc-
cupation and timing analysis were presented after application of hardware-software
co-design.
The elliptic curve method implementation in hardware The security of
the most applied public-key cryptographic algorithm – RSA depends on hardness
of factoring large numbers. In the currently best known method for factoring large
integers – the GNFS one important step is the factorisation of mid-sized integers
for which an ECM is an efficient algorithm.
The ECM algorithm is a classical example of algorithm that can be significantly
accelerated thanks to special-purpose hardware. We provided a detailed description
of efficient ECM architecture, especially suited for hardware implementation. The
modular multiplier obtained as a result of our research described in the previous
point presents a core element of the ECM unit and allows fast prototyping. For
124