1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
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FEI KEMT<br />
the sequence, altogether ϕ(D) + 6 numbers. The computational costs consist of the<br />
generation of T and the calculation of mDQ which amounts to at most D<br />
4<br />
+ B2<br />
D<br />
elliptic curve operations (mostly additions) and at most 3(π(B2) − π(B1)) modular<br />
multiplications, π(x) be<strong>in</strong>g the number of primes up to x. The last term can be<br />
lowered if D conta<strong>in</strong>s many small prime factors s<strong>in</strong>ce this will <strong>in</strong>crease the number<br />
of pairs (m, k) for which both mD − k and mD + k are prime. Neglect<strong>in</strong>g space<br />
considerations a good choice for D is a number around √ B2 which is divisible by<br />
many small primes.<br />
4 Elliptic Curve Method <strong>in</strong> <strong>Hard</strong><strong>ware</strong><br />
We present the first published hard<strong>ware</strong> implementation of the ECM for <strong>in</strong>teger fac-<br />
tor<strong>in</strong>g. The ECM implementation <strong>in</strong>cludes a complete hard<strong>ware</strong> logic that supports<br />
the ECM factor<strong>in</strong>g of numbers up to approximately 200 bits. The proposed solution<br />
applies parameters best suited to f<strong>in</strong>d factors of up to about 42 bits. The ECM<br />
design features a support<strong>in</strong>g logic for computation of the modular operations as ad-<br />
dition, subtraction, multiplication and squar<strong>in</strong>g. The multiplication and squar<strong>in</strong>g<br />
is computed <strong>in</strong> the MMM unit analysed <strong>in</strong> the Chapter 2. The circuit has a good<br />
scalability also to larger and smaller bit lengths. For a proof-of-concept purpose,<br />
the ECM architecture has been implemented as a soft<strong>ware</strong>-hard<strong>ware</strong> co-design on a<br />
FPGA and an embedded micro-controller <strong>in</strong> a SOC. Such a design perfectly fits the<br />
needs of recent proposals for hard<strong>ware</strong> architectures for the GNFS (see, e.g. [64])<br />
and can reduce the overall costs of a GNFS device considerably.<br />
Parts of this section were published <strong>in</strong> papers [65,94,120]. The research achieve-<br />
ments described <strong>in</strong> this chapter <strong>in</strong>clude the follow<strong>in</strong>g:<br />
• ECM algorithm for hard<strong>ware</strong> – algorithm adaptation and parametrisation,<br />
• ECM implementation – unit design, parallelisation, case study for GNFS.<br />
The ECM implementation was done as a jo<strong>in</strong>t work, ma<strong>in</strong>ly with Jan Pelzl from<br />
Ruhr University Bochum (<strong>in</strong> SHARK project that <strong>in</strong>cludes the ECM design, have<br />
cooperated also Christ<strong>in</strong>e Priplata and Col<strong>in</strong> Stahlke (Edizone GmbH, Germany),<br />
and Jens Franke and Thorsten Kle<strong>in</strong>jung (University of Bonn, Germany)).<br />
The Section 4.1 describes the details on selection of the parameters <strong>in</strong> the ECM.<br />
The architecture of the implementation and discussion on the chosen algorithms<br />
for the modular operations is presented <strong>in</strong> the Section 4.2. Implementation details<br />
55<br />
+ 7