1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
Status and Control Interface The operations inside the MMM coprocessor are
controlled by a control register that is mapped in the control unit’s memory via the
interface. In the presented solution there are two control bits:
bit 0 controls the multiplication/squaring process. Set 1 to trigger the computa-
tions, 0 for idle.
bit 1 switches between the multiplication and squaring. Set 0 to compute the MMM
on the input parameters X and Y , set 1 to square (multiple the operand by
itself) the value stored in memory register Y .
A status register has been used to check the actual status of the coprocessor and
the computational process in the solution published in [117]. The LSB raises during
the data storing and computations. After triggering the computation the processor’s
duty is to check the status register regularly. Once the operation of multiplication or
squaring had been finished the value of the status bit is changed to 0. The control
unit is expected to read the results from the MMM coprocessor and, if required,
repeat the operation with new operands.
The version described in [49] uses the communication over an interrupt (signal
irq in Figure 2 – 7). This solution is more suitable for software control of coprocessors
and for a configuration with several MMM coprocessors. After the computation of
the MMM the interrupt signal of the host processor is asserted. This state persists
until the results are read within the interrupt routine by the processor. Thereafter
new operands can be loaded into the memory and the whole process started again.
Memory Operations The transfer of the operands between the control unit and
the coprocessor is executed by a couple of control signals (chip select denoting the
particular coprocessor, and write enable signalising a storing operation) and buses
for address and data.
The syntax of operand address has been explained in Table 2 – 1. The chip select
signal of the corresponding coprocessor is asserted according to the address decoded
by the interface. Since the input operands X, Y and M require only access for
their storage and on the other hand the operand S is exclusively used as the output
register of the coprocessor, their addresses may be shared. The particular operand
register is then selected as per write enable signal and the addresses.
In case when the internal word widths of the processor and the coprocessor do
not match, an additional functionality is required from the interface to perform the
memory alignment and proper decoding of the memory address.
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