1 Montgomery Modular Multiplication in Hard- ware

List of Figures
1 – 1 Typical architecture of the smallest functional unit in a FPGA. . . . 6
1 – 2 RSA encryption scheme when A sends encrypted message to B. First
A receive B’s public key upon a request, afterwards A encrypts a
message X using the B’s public key Y = X E mod M. Finally B
decrypts the received message Y using own private key X = Y D mod
M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 – 1 Architecture of a general scalable coprocessor based on separate mem-
ory and ALU connected by w-bit data-path . . . . . . . . . . . . . . 21
2 – 2 One level of the w-bit adder implemented as CPA and CSA with FAs 27
2 – 3 Block diagram of the CSA-based w-bit MWR2MM processing element
(CSA PE) based on FA . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 – 4 Block diagram of CPA-based w-bit MWR2MM processing element
(CPA PE) based on FA . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 – 5 Pipelined organization of the MMM coprocessor based on n-stage PEs
connection and separated embedded data memory . . . . . . . . . . . 30
2 – 6 Organisation of the dual-port memory register inside the MMM co-
processor for one variable with e words of width w bits . . . . . . . . 32
2 – 7 Proposed universal interface for the MMM coprocessor . . . . . . . . 34
4 – 1 Architecture of the ECM unit . . . . . . . . . . . . . . . . . . . . . . 58
4 – 2 Organisation of the ECM unit’s memory registers for 21 variables
with e words of width w . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 – 3 Scalable addition and subtraction unit for operands with word width w 63
5 – 1 Schematic diagram of a TRNG with designation of internal signals
and interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5 – 2 Illustration of stable states (0 and 1) and undefined metastable state 78
5 – 3 Timing jitter in clock signal . . . . . . . . . . . . . . . . . . . . . . . 81
5 – 4 Ring oscillator structures proposed by Golić. . . . . . . . . . . . . . . 83
5 – 5 Block structure of the PLL-TRNG with two PLLs, sampling gate and
corrector of the output sequence. . . . . . . . . . . . . . . . . . . . . 86
5 – 6 Sampling of the CLJ clock signal including the tracking jitter on the
raising edge of the CLK signal (illustrated for KM = 5 and KD = 7) 86
6 – 1 Block diagram of analog PLL circuitry for clock signal synthesis in
Altera FPGA [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95