1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
Table 6 – 7 Area occupation of one PLL TRNG with delay line in FPGA Actel ProASICPlus
parameters:
• FCLK = FCLI = 40 MHz
Logic type Number Usage
Core Cells 396 4.8%
FIFO Cells 2 6.3%
PLLs 1 50%
• FCLJ = MCLJ
DCLJ FCLI = 1240
= 68.5714 MHz
• Number of delay elements (NAND gates): 8
7
• Accumulation period: 17TQ = 119 periods of FCLK
The requirements for the area occupation are summarised in Table 6 – 7. The
design includes also the logic for reading the internal signals and generated sequence
by a computer and can be reduced if required.
The NIST statistical tests were performed on continuous 1-Gigabit TRNG out-
put records and followed the testing strategy, general recommendations, and result
interpretation described in [97]. We have used a set of 1000 1-Megabits sequences
produced by the TRNG, for which most of the tests were passed, however, some
of them do not e.g. overlapping template test or some variants of non-periodic
templates. Considering the fact that the generated sequence is in some parame-
ters slightly distinguishable from truly random stream may signalise some problems
inside the TRNG implementation, on the other hand, the tested sequence is ex-
tremely long (1 gigabit continual record) unlike the output streams required for
practical applications.
The experimental tests of configurations with two PLLs connected in parallel or
cascade have shown, that the condition expressed by Equation 5.6 is necessary but
not sufficient condition for proper running of the TRNG. From the results we can
prove, confirming the theoretical analysis, that the tracking jitter can be sampled
and the generator includes critical random samples. But to achieve reliably an unbi-
ased and random sequence the number of the critical samples and their probability
distribution have to satisfy some additional conditions that will be specified later in
this chapter.
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