1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
change, but the time for data I/O scales linearly with the number of units. Hence,
not too many units should be controlled by one single logic. For massively parallel
ECM in hardware, the ECM units can be segmented into clusters, each with its own
control unit.
4.3 Implementation of the ECM Unit
This section presents the actual hardware implementation done on a SOC (FPGA
and embedded microprocessor). This first hardware implementation of ECM is de-
signed as a proof-of-concept. All timings are obtained by using real hardware, not
only simulation. All results have been carefully checked by a reference implementa-
tion in software.
4.3.1 Hardware Platform
The ECM implementation is realized as a hybrid design. It consists of an ECM
unit implemented on an FPGA (Xilinx Virtex2000E-6) [124] and a control logic
implemented in software on an embedded micro-controller (ARM7TDMI, 25MHz)
[90]. The ECM unit is coded in VHDL and was simulated and synthesised for the
FPGA by using FPGA Advantage tools, place & route was done in Xilinx ISE. For
the actual VHDL implementation, memory cells have been realized with the FPGA’s
internal block RAM. For the word width w = 32 bits 2 blocks with e = ⌈ N+1⌉
words
2
are used for each register due to dual-port access mode and selected algorithm for
multiplication.
The ECM unit, as implemented, expects the commands which are written to a
control register accessible by the embedded ARM processor. Required point coordi-
nates and curve parameters are loaded into the ECM unit before the first command
is decoded. For this purpose, these memory cells of unit are accessible from the
outside by a unique address. Internal registers, which are only used as temporary
registers during the computation are not accessible from the outside, by the micro-
controller.
The control of the whole unit is done by the micro-controller present on the
board. The processor controls the data transfer from and to the units, and issues
the commands for all steps in phase 1 and phase 2 for the central control login inside
FPGA. For code generation, debugging and compilation, the ARM Developer Suite
1.2 was used. For details on the ARM microprocessor, see [23]. At a later stage,
a soft-core processor core (in VHDL) could be used instead of an hard-wired ARM
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