1 Montgomery Modular Multiplication in Hard- ware

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FEI KEMT reference edge mean period unit interval jitter Figure 5 – 3 Timing jitter in clock signal Cycle-to-cycle jitter is the difference in a clock’s period from one cycle to the next one. Cycle-to-cycle jitter is the most difficult to measure usually requiring a timing interval analyser. Half-period jitter is the measure of maximum change in a clock’s output transition from its ideal position during one-half period. Period jitter is the change in a clock’s output transition, typically the rising edge, from its ideal position over consecutive clock edges. Period jitter is measured and expressed in time or frequency. Period jitter measurements are used to calculate timing margins in systems. Tracking jitter is defined as a variation in time relationship between the edges of the reference (input) clock and output clock of a clock circuitry. Deterministic periodic jitter is typically caused by external deterministic noise sources coupling into a system, such as switching power-supply noise or a strong local radio frequency carrier. It may also be caused by an unstable clock-recovery PLL. While a random process can, in theory, have any probability distribution, random jitter is assumed to have a Gaussian distribution for the purpose of the jitter model. One reason for this is that the primary source of random noise in many electrical circuits is thermal noise (also called Johnson noise or shot noise), which is known to have a Gaussian distribution. Another, more fundamental reason is that the composite effect of many uncorrelated noise sources, no matter what the distributions of the individual sources approaches a Gaussian distribution according to the central limit theorem [107]. For a random signal with a Gaussian distribution, there is theoretically no limit on the max and min values, so the observed peak-peak value will generally grow 81
FEI KEMT over time. For this reason, the peak-peak value should be used in conjunction with the population size and some knowledge of the type of distribution. 5.2.2 Survey of Designs Based on Jitter In this section we summarise currently most known concepts and designs of genera- tors based on extraction of randomness from clock jitter. The jitter appears in clock signals generated by free-running oscillators or PLL circuitry implemented inside a digital device. The Tkacik TRNG Design The generator invented by Tkacik [111] includes combination of two deterministic circuits – a linear feedback shift register (LFSR) and cellular automation shift register (CASR). The registers are clocked by two inde- pendent rings whose clock frequency is influenced by external impacts and includes jitter. In addition, the selected outputs of CASR and LFSR are XORed together providing the final random signal. The harvesting technique of the generator is very complex and no verification of its effectiveness is provided. The design was evaluated by Dichtl [43] who pointed out an issue with unclear source of randomness in the generator. Under certain conditions and with partial knowledge of some internal values an attacker is able to predict the generated value due to low level of entropy. The Fischer and Drutarovsk´y Design In design from Fischer and Drutarovsk´y [60] the idea is to extract random values by sampling a clock signal influenced by tracking jitter caused by analogue PLL in FPGAs from Altera. The jitter can be sampled only under defined condition when frequencies of sampled and sampling clock signals are in a certain ratio. Sampling of clock signal is executed periodically with period given by PLL di- viders. Samples taken in transition zones have nonzero probability to result in logical one or zero and are called critical samples. The position of critical samples is stabilised during operation of the generator as far as the working conditions of the generator do not change. More details on the TRNG implementation and features of the generator are described in the next section. This design provide us a reference for theoretical testing and theories which are presented in the thesis. 82
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Technical University of Koˇsice Fa
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Metadata Sheet Author: Martin ˇ Si
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FEI KEMT ciel’ovej platformy a vl
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Acknowledgement There are several p
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Contents Introduction 1 1 Montgomer
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FEI KEMT 6.2.3 Analysis of TRNG in
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FEI KEMT 6 - 2 Block diagram of dig
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List of Algorithms 1 - 1 Montgomery
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FEI KEMT π(p) prime counting funct
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FEI KEMT MWR2MM Multiple Word Radix
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FEI KEMT and Elliptic Curve Cryptog
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FEI KEMT The hardware implementatio
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FEI KEMT data inputs clock Look-up
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FEI KEMT A (X) request for B’s pr
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FEI KEMT Algorithm 1 - 1 Montgomery
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FEI KEMT In the Algorithm 1 - 1 the
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FEI KEMT by the radix b changes to
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FEI KEMT the ECC instead of the RSA
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FEI KEMT Algorithm 1 - 5 Key genera
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FEI KEMT 2 Montgomery Modular Multi
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FEI KEMT not significant. On the ot
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FEI KEMT Algorithm 2 - 2 The multip
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FEI KEMT Beside the internal struct
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FEI KEMT q x i S (j) 2 w-1 S (j) 1
Page 49 and 50: FEI KEMT x i x i-1 xi-n+1 Y (j) M (
Page 51 and 52: FEI KEMT especially if the access t
Page 53 and 54: FEI KEMT 2.2.3 Interface to Control
Page 55 and 56: FEI KEMT Clock Signal Distribution
Page 57 and 58: FEI KEMT 2.3.2 Montgomery Multiplic
Page 59 and 60: FEI KEMT 1. Fully software solution
Page 61 and 62: FEI KEMT 2.3.4 Implementation Resul
Page 63 and 64: FEI KEMT 3 Elliptic Curve Method in
Page 65 and 66: FEI KEMT improving the area-time pr
Page 67 and 68: FEI KEMT 3.3.1 Pollard’s (p − 1
Page 69 and 70: FEI KEMT If the order of P ∈ E(Fq
Page 71 and 72: FEI KEMT handicap of the Montgomery
Page 73 and 74: FEI KEMT Two major improvements hav
Page 75 and 76: FEI KEMT and case study with GNFS b
Page 77 and 78: FEI KEMT Table 4 - 1 Computational
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Page 81 and 82: FEI KEMT Algorithm 4 - 1 Modified M
Page 83 and 84: FEI KEMT Algorithm 4 - 2 Modular ad
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Page 95 and 96: FEI KEMT control also all the syste
Page 97 and 98: FEI KEMT we can mention a generator
Page 99: FEI KEMT noise to binary signal a c
Page 103 and 104: FEI KEMT The Bucci and Luzzi Testab
Page 105 and 106: FEI KEMT CLI PLL PLL 1 2 CLJ CLK D
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Page 109 and 110: FEI KEMT extraction. In other words
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Page 113 and 114: FEI KEMT 6 True Random Number Gener
Page 115 and 116: FEI KEMT clock input F IN F FB Phas
Page 117 and 118: FEI KEMT Table 6 - 2 Parameters of
Page 119 and 120: FEI KEMT Since the size of the jitt
Page 121 and 122: FEI KEMT Table 6 - 3 Parameters set
Page 123 and 124: FEI KEMT where N1 is the number of
Page 125 and 126: FEI KEMT oscillator with frequency
Page 127 and 128: FEI KEMT Table 6 - 7 Area occupatio
Page 129 and 130: FEI KEMT 0,75 0,5 0,25 1 0 1 30 59
Page 131 and 132: FEI KEMT Stochastic Model The clock
Page 133 and 134: FEI KEMT Table 6 - 8 Mean values me
Page 135 and 136: FEI KEMT Figure 6 - 8 Sampled wavef
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Page 139 and 140: FEI KEMT Figure 6 - 11 Amount of sa
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Page 143 and 144: FEI KEMT 7 Research Contribution Wi
Page 145 and 146: FEI KEMT Curriculum vitae Professio
Page 147 and 148: FEI KEMT [16] Altera Corporation. S
Page 149 and 150: FEI KEMT [37] Bundesamt für Sicher
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FEI KEMT [54] Federal Information P
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FEI KEMT [71] Gura, N., Chang, S.,
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FEI KEMT of Commerce, month = aug,
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FEI KEMT and C. Paar, Eds., no. 216
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FEI KEMT [128] Zimmermann, P. ECMNE
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1 Montgomery Modular Multiplication in Hard- ware

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