1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
The clock conditioning circuits usually enable to perform following functions (in
dependency on FPGA vendor and family): clock phase adjustment, clock delay
minimisation, clock frequency synthesis, clock modulation spread-spectrum, static
or dynamic configuration of circuits parameters, etc.
We explain two mostly applied principles for clock signal management in FPGAs
based on PLL and delay-locked loop (DLL). Both principles can be implemented
as digital or analog circuits. While the FPGA vendor Xilinx has chosen digital
implementation of DLL in most of their FPGAs, other vendors like Altera and
Actel included in their devices a clock circuitry based on an analog PLL.
Phase-Locked Loop Circuitry Typical analog PLL block in Altera and Actel
devices (see Figure 6 – 1) can provide at least one synthesised clock signal with
frequency FOUT :
FOUT = FV CO
k
= FREF
m
k
= FIN
m
n × k
, (6.1)
where FIN is the frequency of the input clock source that can be an external crystal
or other PLL in case of PLL cascade, FREF is the input reference frequency that
is used to lock the feedback clock FF B, and finally the voltage controlled oscillator
(VCO) produces a clock signal with output frequency FV CO. Reference-, feedback-
and post-divider values n, m, and k can vary from one to several hundreds in
FPGAs [11, 14], or to several thousands in ASICs [22] and set together with VCO
working limits the range of input and output frequencies.
clock
input
F IN
:n
F REF
F FB
Phase
Frequency
Detector
:m
Charge
Pump
Loop
Filter
&
VCO
F VCO
:k
.
.
.
:k
1
c
clock
output(s)
Figure 6 – 1 Block diagram of analog PLL circuitry for clock signal synthesis in Altera FPGA [11]
Delay-Locked Loop Circuitry Synthesis of clock signal in DLL circuits is achieved
by insertion of a variable delay between the input and output clock signal (see Fig-
ure 6 – 2). Delay lines can be built using a voltage controlled delay or as a series of
discrete delay elements as it is in Xilinx DLL [125, 126].
95
F OUT