1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
consequence the RNG designs should provide a testing method designed particularly
for given type of RNG (see e.g. [36]).
In [26] the authors improve modeling of RO TRNG, and instead of conventional
time-based models they provide a phase-oriented presentation. The observation
claiming that the ROs tend to couple with each other have been confirmed by the
experiments with global deterministic jitter. Instead of conclusion that coupling
reduces the randomness of a TRNG, the authors warn of overestimation of the
jitter size. After removing the impact of global jitter the accumulation of jitter is
much slower, what implies in lower sampling frequency of the generator in order to
accumulate obtain random sequences.
5.3 PLL-Based TRNG on FPGA
In this section we introduce TRNG implementation based on randomness extrac-
tion from tracking jitter that is inherent in clock signal produced by analog PLL
embedded in some FPGA families. The PLL circuitry normally applied for synthesis
of on-chip clock signals derived from external quartz signal is driven to provide a
couple of signals with certain fixed ratio of their frequencies. The ratio is selected
for purpose of the jitter sampling and sets also other parameters of the generator as
speed of output random sequence.
In the following pages we compile dependencies between the PLL and TRNG
parameters and explain their meaning. We explain the fundamental method behind
the PLL-based TRNG (PLL-TRNG) invented by Fischer and Drutarovsk´y and pub-
lished in [60].
5.3.1 Randomness Extraction Method
The tracking jitter in the output signal of the on-chip analog PLL is detected by
sampling the signal using an other rationally related clock signal. The fundamental
issue of allowing jitter sampling lies in setting of the sampled and sampling edges
close enough to each other. When this condition is met, the unpredictable jitter
decides on the output values of the sampling gate. The simplified structure of the
PLL-TRNG is depicted in Figure 5 – 5.
Let us have two clock signals CLK and CLJ with frequencies FCLJ and FCLK
in the given ratio:
FCLJ
FCLK
= KM
KD
= MCLJDCLK
MCLKDCLJ
85
, (5.2)