1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
References
[1] Actel Corporation. ProASICplus Evaluation Board, User’s guide, 2002.
[2] Actel Corporation. Axcelerator Family PLL and Clock Management, Ap-
plication Note, June 2003.
[3] Actel Corporation. Using ProASICplus Clock Conditioning Circuits, Ap-
plication Note, Dec. 2004.
[4] Actel Corporation. ProASIC3(E) Flash Family FPGAs, Datasheet, Jan.
2005.
[5] Actel Corporation. ProASICplus Flash Family FPGAs, ver. 5.3, May
2006.
[6] Altera Corporation. Metastability in Altera Devices ver.4.0, May 1999.
[7] Altera Corporation. ACEX 1K Programmable Logic Device Family, Data
Sheet, Sept. 2001. ver. 3.3.
[8] Altera Corporation. APEX 20K Programmable Logic Device Family,
Data Sheet, Feb. 2002. ver. 4.3.
[9] Altera Corporation. Avalon Bus Specification, Reference Manual, Jan.
2002. ver. 2.0.
[10] Altera Corporation. Nios Embedded Processor Development Board
ver.2.1, Apr. 2002.
[11] Altera Corporation. Using PLLs in Stratix Devices, Feb. 2002. ver. 1.0.
[12] Altera Corporation. Cyclone Device Handbook, Using PLLs in Cyclone
Devices, Oct. 2003. ver. 1.2.
[13] Altera Corporation. Cyclone Programmable Logic Device Family, Data
Sheet, Mar. 2003. ver. 1.1.
[14] Altera Corporation. Using the ClockLock & ClockBoost PLL Features in
APEX Devices, Nov. 2003. Application Note 115, ver. 2.6.
[15] Altera Corporation. Stratix Device Handbook, General-Purpose PLLs in
Stratix & Stratix GX Devices, Sept. 2004. ver. 3.1.
127