1 Montgomery Modular Multiplication in Hard- ware

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Preface Systems for public key cryptography are intensively applied in order to digitally sign or encrypt data. In this way we assure integrity and confidentiality of the signed message and provide authentication and non-repudiation features for a signer. The complexity of computations has impact on performance of the system, especially in case of long keys. The security of the operations is based on secrecy of the private key, while its public part and the algorithm itself are publicly known. In the first part of thesis we analyse the computational part of the systems and focus on flexible implementation of modular multiplier. The output of the research was applied in order to estimate performance of Elliptic Curve Method (ECM) increased thanks to its hardware realisation. Scalable nature of the multiplier was spread in the whole design, and the proof-of-concept implementation was designed and tested in a very short time. In the second part of document we focus on the key generating element – a Ran- dom Number Generator (RNG). Already known design was analysed under several aspects and we provide results in the form of a stochastic model of the RNG and proposed testing methods suitable for this type of RNGs. The target platform for the selected building blocks of cryptosystems is FPGA (Field Programmable Gate Array) what offers a reduction of development time, wide range of devices and high level of security. In the thesis analyse particular families of devices from FPGA vendors which include dedicated electronic elements used in our designs. Parameters of the blocks and algorithm improvements may have significant impact on the performance of system. Three topics of the thesis provide a picture of complexity level in cryptology and underline relevance of research in area of cryptographic systems implementation.
Contents Introduction 1 1 Montgomery Modular Multiplication in Hardware - preliminaries 3 1.1 Implementation Platforms . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 RSA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2.1 Modular Exponentiation and Multiplication . . . . . . . . . . 8 1.2.2 Hardware Implementations of the MMM . . . . . . . . . . . . 12 1.3 EC in Cryptography . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 Montgomery Modular Multiplication in Hardware 20 2.1 Scalable MMM design . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.1 Scalable Multiple-Word Algorithms . . . . . . . . . . . . . . . 22 2.1.2 Comparison of Implementation Approaches . . . . . . . . . . . 23 2.2 Multiplier Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.1 Adder Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.2 Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.3 Interface to Controller . . . . . . . . . . . . . . . . . . . . . . 34 2.3 Implementation of the MMM . . . . . . . . . . . . . . . . . . . . . . 36 2.3.1 Comparison of CSA and CPA PE . . . . . . . . . . . . . . . . 36 2.3.2 Montgomery Multiplication Coprocessor . . . . . . . . . . . . 38 2.3.3 Hardware-Software Co-design of MMM: a Case Study . . . . . 38 2.3.4 Implementation Results . . . . . . . . . . . . . . . . . . . . . 42 2.4 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . 42 3 Elliptic Curve Method in Hardware - preliminaries 44 3.1 Integer Factoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.1 Factoring Algorithms . . . . . . . . . . . . . . . . . . . . . . . 44 3.1.2 Motivation for Hardware Implementation . . . . . . . . . . . . 45 3.2 Previous Implementations of ECM . . . . . . . . . . . . . . . . . . . 46 3.3 Mathematical Background . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.1 Pollard’s (p − 1)-algorithm . . . . . . . . . . . . . . . . . . . . 48 3.3.2 ECM Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Page 1 and 2: Technical University of Koˇsice Fa
Page 3 and 4: Metadata Sheet Author: Martin ˇ Si
Page 5 and 6: FEI KEMT ciel’ovej platformy a vl
Page 7: Acknowledgement There are several p
Page 11 and 12: FEI KEMT 6.2.3 Analysis of TRNG in
Page 13 and 14: FEI KEMT 6 - 2 Block diagram of dig
Page 15 and 16: List of Algorithms 1 - 1 Montgomery
Page 17 and 18: FEI KEMT π(p) prime counting funct
Page 19 and 20: FEI KEMT MWR2MM Multiple Word Radix
Page 21 and 22: FEI KEMT and Elliptic Curve Cryptog
Page 23 and 24: FEI KEMT The hardware implementatio
Page 25 and 26: FEI KEMT data inputs clock Look-up
Page 27 and 28: FEI KEMT A (X) request for B’s pr
Page 29 and 30: FEI KEMT Algorithm 1 - 1 Montgomery
Page 31 and 32: FEI KEMT In the Algorithm 1 - 1 the
Page 33 and 34: FEI KEMT by the radix b changes to
Page 35 and 36: FEI KEMT the ECC instead of the RSA
Page 37 and 38: FEI KEMT Algorithm 1 - 5 Key genera
Page 39 and 40: FEI KEMT 2 Montgomery Modular Multi
Page 41 and 42: FEI KEMT not significant. On the ot
Page 43 and 44: FEI KEMT Algorithm 2 - 2 The multip
Page 45 and 46: FEI KEMT Beside the internal struct
Page 47 and 48: FEI KEMT q x i S (j) 2 w-1 S (j) 1
Page 49 and 50: FEI KEMT x i x i-1 xi-n+1 Y (j) M (
Page 51 and 52: FEI KEMT especially if the access t
Page 53 and 54: FEI KEMT 2.2.3 Interface to Control
Page 55 and 56: FEI KEMT Clock Signal Distribution
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FEI KEMT 1. Fully software solution
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FEI KEMT 2.3.4 Implementation Resul
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FEI KEMT 3 Elliptic Curve Method in
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FEI KEMT improving the area-time pr
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FEI KEMT 3.3.1 Pollard’s (p − 1
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FEI KEMT If the order of P ∈ E(Fq
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FEI KEMT handicap of the Montgomery
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FEI KEMT Two major improvements hav
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FEI KEMT and case study with GNFS b
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FEI KEMT Table 4 - 1 Computational
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FEI KEMT from or writing to a singl
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FEI KEMT Algorithm 4 - 1 Modified M
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FEI KEMT Algorithm 4 - 2 Modular ad
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FEI KEMT microprocessor, e.g. Alter
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FEI KEMT timings of ECM implementat
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FEI KEMT hardware was implemented o
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FEI KEMT [68] what can be expressed
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FEI KEMT and a harvesting mechanism
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FEI KEMT control also all the syste
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FEI KEMT we can mention a generator
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FEI KEMT noise to binary signal a c
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FEI KEMT over time. For this reason
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FEI KEMT The Bucci and Luzzi Testab
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FEI KEMT CLI PLL PLL 1 2 CLJ CLK D
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FEI KEMT For R it holds that the in
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FEI KEMT extraction. In other words
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FEI KEMT and effort needed for repr
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FEI KEMT 6 True Random Number Gener
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FEI KEMT clock input F IN F FB Phas
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FEI KEMT Table 6 - 2 Parameters of
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FEI KEMT Since the size of the jitt
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FEI KEMT Table 6 - 3 Parameters set
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FEI KEMT where N1 is the number of
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FEI KEMT oscillator with frequency
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FEI KEMT Table 6 - 7 Area occupatio
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FEI KEMT 0,75 0,5 0,25 1 0 1 30 59
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FEI KEMT Stochastic Model The clock
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FEI KEMT Table 6 - 8 Mean values me
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FEI KEMT Figure 6 - 8 Sampled wavef
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FEI KEMT Table 6 - 9 Results of sta
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FEI KEMT Figure 6 - 11 Amount of sa
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FEI KEMT Figure 6 - 13 Amount of sa
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FEI KEMT 7 Research Contribution Wi
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FEI KEMT Curriculum vitae Professio
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FEI KEMT [16] Altera Corporation. S
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FEI KEMT [37] Bundesamt für Sicher
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FEI KEMT [54] Federal Information P
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FEI KEMT [71] Gura, N., Chang, S.,
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FEI KEMT of Commerce, month = aug,
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FEI KEMT and C. Paar, Eds., no. 216
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FEI KEMT [128] Zimmermann, P. ECMNE
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