1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
6.2.2 Analysis of TRNG in Altera Stratix FPGAs
Our implementation strategy for the described case was to get the fastest and the
best quality generator using a minimum amount of resources (PLLs). Since the
Stratix family contains two types of PLLs, several configurations are possible.
The most economic solution would be based on the use of one FPLL (since there
are four FPLLs in the chosen device). But the multiplication and division factors
of a single FPLL cannot fulfil the implementation condition (5.6). Other option is
to use EPLL with extended range of parameters that enables to build a single-PLL
TRNG. For this reason, following four architectures of the TRNG implemented in
Altera Stratix devices are possible:
1. Two FPLLs (referenced further as configuration A)
2. One FPLL and one EPLL (configuration B)
3. One EPLL (configuration C)
4. Two EPLLs (configuration D)
The relationship between the sensibility on the jitter S and the output bitrate
R of the TRNG for configuration with 2 parallel PLLs (see Table 6 – 3 for other
configurations and characteristic parameters) was described in equations 5.8 and
5.9.
Experimental Results TRNG architectures were tested on Altera DSP board
with Stratix EP1S25F780C5 [16]. The TRNG architectures were described in VHDL
and implemented using Altera Quartus II development system, version 3.0 SP2.
Acquired bits were transmitted to the PC through a parallel port. The complete
TRNG design including 1024 x 8-bit FIFO and a parallel interface controller needs
up to 120 LEs from about 25000 LEs available in the device. The signal CLK was
used as a clock signal for the control logic and was therefore limited to about 250
MHz (although the output frequency of the PLL can be higher).
In order to test basic quality of different versions of TRNG, we evaluated the
following statistical parameters of the generated bit sequence b(n) (all of them were
computed for the record length of N = 1000000 bits):
1. Bias computed as
bias = E[b(n)] − 0.5 = E[b] − 0.5 ∼ = N1
N
103
− 0.5 (6.2)