1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
2.3.2 Montgomery Multiplication Coprocessor
Having the optimised PE for the MMM computations our objective is to complete
the MMM coprocessor with all necessary parts. The memory registers, the interface
to the control unit and the clock distribution logic are integral parts of the MMM
coprocessor. The IP block including all mentioned design units is very suitable for
quick system development providing the full functionality for operations demanding
the MMM and a universal interface for connection to the control processor.
The architecture of the coprocessor and all its parts has been discussed in the
Section 2.2. In the Table 2 – 4 we provide the results for the area occupation and
the critical path expressed as the maximal clocking frequency on the Altera APEX
20K200E FPGA. For the sample configuration we have chosen the MMM coprocessor
based on the multiplier unit based on the MWR2MM CSA Algorithm with operands
word width (w = 32) and precision k = 1024 and k = 2048 bits, respectively.
Table 2 – 4 Area occupation in number of LEs and maximal clock frequency (fclkMMM ) (MHz) of
the MMM coprocessor (w = 32, n = 1..4) with MWR2MM CSA algorithm
k = 1024 k = 2048
LEs (fclkMMM ) (LEs) (fclkMMM )
n = 1 542 107.22 551 105.83
n = 2 1100 110.43 1136 106.96
n = 3 1621 108.34 1644 104.39
n = 4 1943 106.67 1980 103.85
2.3.3 Hardware-Software Co-design of MMM: a Case Study
For configurable platform is typical a SOC architecture. Such approach reduces
the production costs and on the other hand provides very suitable platform for the
cryptographic applications. The SOC minimises the number of external interfaces
and in this way decreases also the amount of leaked information.
Another advantage of use of the SOC is that hardware and software solutions can
be compared in a better way. Therefore the choice of optimal resources utilisation
is based on a proper analysis. In the SOC both software and hardware solutions
occupy the same resources.
The fully software solution usually needs relatively large logic resources and small
memory resources to implement the processor and sometimes large memory to im-
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