1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
as a (deterministic) jitter.
We analyse further the parameters of PLL circuits in Stratix family of Altera
FPGAs and their relations to the generated clock signal and jitter included in it.
The Altera Stratix devices include two types of PLLs:
Fast PLL (FPLL): Stratix devices include up to 8 FPLLs. The FPLLs offer
general-purpose clock management with multiplication and phase shifting.
The multiplication is simplified in comparison to EPLL and uses only m/k
scaling factors with a range from 1 to 32 [15]. Input frequency can vary in
dependency on m (for speed grade -5) from 15 to 717 MHz, output frequency
from 9.4 to 420 MHz, and the frequency of the VCO from 300 to 1000 MHz.
Enhanced PLL (EPLL): Comparing to FPLL, the EPLLs have some additional
configurable features like external feedback, configurable bandwidth, run-time
reconfiguration, etc. and have enhanced range of parameters. Input frequency
can vary (for a speed grade -5 device) from 3 to 684 MHz, output frequency
from 9.4 to 420 MHz and the frequency of the VCO from 300 to 800 MHz.
Reference-, feedback- and post-divider values n, m and k can vary from 1 to
512 (1024 for k) with 50% duty cycle [15].
The size of the intrinsic jitter of the PLL depends on the quality factor Q of the
VCO, on the bandwidth of the loop filter (see Figure 6 – 1), and on the so-called
pattern jitter introduced by the phase frequency detector. The technology of the
PLL and the quality of the VCO is given by FPGA design. A designer can change
the output jitter directly - by modification of scaling factors (for FPLL and EPLL)
and filter bandwidth (only for EPLL), but also indirectly by the design of the board
(separation of the analog and digital ground, filtering of the analog power supply,
etc.).
PLL acts as a low-pass filter, therefore a low bandwidth setting of the lop filter
can be applied to filter out high frequency jitter from the input clock. To track the
input jitter, one can use a high bandwidth setting. As mentioned already a power
supply noise could cause the VCO output frequency to fluctuate and cause jitter. In
such cases a low bandwidth causes the feedback loop to respond slower to the noise
being injected by the VCO. In turn, it cannot adjust for this noise and counteract it.
A high bandwidth allows the loop to respond quickly to the noise and compensate
for it. Therefore there is a tradeoff between high and low pass filter of PLL loop
filter that causes either filtering of the input signal jitter or VCO noise.
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