1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
Figure 6 – 12 Amount of sampled ones during 1000 sampling periods according to temperature
for chosen sample positions in TRNG with configuration A.
By theoretical and practical analysis we concluded that the PLL circuitry is
more suitable for discussed TRNG implementation when compared to DLL. The
parameters of the PLL circuitry available in FPGAs present on the market are
satisfactory for reliable implementation. We showed the steps for theoretical analysis
of the PLL parameters with estimation of the jitter and TRNG parameters that were
later confirmed by empirical measurements.
Two practical implementations in Altera and Actel families of FPGAs showed
which criteria are important in the design. The achieved final speed of the generator
in Altera Stratix device is more than 1Mbit/s with the quality of output confirmed
by statistical tests. Thanks to the analysis of available PLL configuration and their
parameters we have presented a generator without additional delaying logic applied
in the original proposal [60]. Application of simpler sampling part of the generator
is possible thanks to wider dividers range of PLL circuits in Stratix FPGA family.
We presented the most compact solution with one PLL circuit and the chain of
delay elements implemented in Actel ProASICplus device. The results of statistical
tests for very long record of generated data confirm high level of randomness, with
few tests failed. We can conclude that it was theoretically and also practically
confirmed that the PLL-TRNG is suitable for fully embedded implementation in
low-cost FPGAs and provides a reliable source of truly random values also in cases
when only a small number of PLLs with limited range of frequency dividers is
available.
The proposed stochastic model of the generator allows to prove the mutual sta-
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