1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
x i x i-1 xi-n+1
Y (j)
M (j)
S (j)
PE 1
Y (j-1)
M (j-1)
S (j-1)
PE 2
S (j-n)
data
memory
. . .
. . .
. . .
Y (j-n+1)
M (j-n+1)
S (j-n+1)
PE n
Figure 2 – 5 Pipelined organization of the MMM coprocessor based on n-stage PEs connection
and separated embedded data memory
The maximum degree of pipeline that can be obtained with this architecture is
found as:
nmax =
� �
e + 1
2
(2.3)
The number 2 in denominator expresses the number of clock cycles after which the
output of the MMM unit is valid. It means also that new values for input variables
of the PEs in the pipelined row are delivered every third clock cycle. Output data
from one stage are kept between the adjacent stages in temporal registers for one
clock cycle and afterwards delivered to the subsequent stage. The stages include the
second register at their input level which provides total delay of two clock cycles as
required by the computation process.
To keep the internal control logic simple the number of the stages n is restricted
to values dividing the number of words e (n|e). Thanks to the simplification in the
moment when the computation had been finished the last word of the sum S is at
the output of the last unit in the row and is directly shifted to the memory to be
stored there. In case of arbitrary n the functionality for a word shift between the
stages at the end of computations would need to be implemented. Addition of the
feature requires some extra logic in the data-path what has a negative influence on
the maximal clock frequency, therefore it is not supported in our designs.
The number of clock cycles needed for a single MMM operation in design con-
taining n ≤ nmax MMM units can be computed as:
TMMM = k2
+ 2n =
wn
� �
ew
e + 2n (2.4)
n
From the Equation 2.4 we can see that the number of stages n has a significant
impact on computation time and reduces it linearly. When less than nmax MMM
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