1 Montgomery Modular Multiplication in Hard- ware

List of Tables
1 – 1 Comparison of the key length (in bits) for equivalent security level
for public-key cryptosystems . . . . . . . . . . . . . . . . . . . . . . . 16
2 – 1 Address of operands from host processor level (LSB right) . . . . . . 33
2 – 2 PE sizes and speeds for old style Altera FPGAs . . . . . . . . . . . . 37
2 – 3 PE sizes and speeds for new style Altera FPGAs . . . . . . . . . . . . 37
2 – 4 Area occupation in number of LEs and maximal clock frequency
(fclkMMM ) (MHz) of the MMM coprocessor (w = 32, n = 1..4) with
MWR2MM CSA algorithm . . . . . . . . . . . . . . . . . . . . . . . . 38
2 – 5 Execution times of software implementation of MMM on Altera Nios
development board (with APEX EP20K200 clocked at 50 MHz) . . . 40
2 – 6 Execution times of mixed hardware-software implementation of MMM
on Altera Nios development board (with APEX EP20K200) for the
CSA PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2 – 7 Execution times of mixed hardware-software implementation of the
MMM on Altera Nios development board (with APEX EP20K200)
for the CPA PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 – 1 Computational complexity and memory requirements for phase 2 de-
pending on D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4 – 2 A command syntax for the ECM unit (LSB left) . . . . . . . . . . . . 59
4 – 3 Running Times of the ECM Implementation (198 bits modulus), p =
2, w = 32 (Xilinx Virtex2000E-6 and ARM7TDMI, 25MHz) . . . . . 67
6 – 1 Parameters of PLL embedded in Altera FPGAs . . . . . . . . . . . . 97
6 – 2 Parameters of PLL embedded in Actel FPGAs . . . . . . . . . . . . . 98
6 – 3 Parameters settings for different TRNG configurations . . . . . . . . 102
6 – 4 Configuration parameters of tested TRNG . . . . . . . . . . . . . . . 105
6 – 5 Results of quality evaluation of tested TRNG configurations . . . . . 105
6 – 6 Achievable sensitivity on jitter using two clock signals in Actel ProA-
SICplus (FCLI = 40MHz) . . . . . . . . . . . . . . . . . . . . . . . . . 107
6 – 7 Area occupation of one PLL TRNG with delay line in FPGA Actel
ProASICPlus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6 – 8 Mean values measured using the stochastic model E[pi] and the out-
put sequence of the TRNG m = E [x(nTQ)] . . . . . . . . . . . . . . . 114
6 – 9 Results of statistical tests (FIPS) of TRNG output and number of
random samples influenced by the jitter at different chip temperatures 118