1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
Table 6 – 2 Parameters of PLL embedded in Actel FPGAs
family # of PLLs dividers range max. output period jitter
ProASIC3(E) 1 (6) NA
ProASICplus 2
Axcelerator 8
180ps for FOUT = 24MHz
90ps for FOUT = 100MHz
70ps for FOUT = 350MHz
m = 1-64 ±1% for FOUT < 10MHz
n=1-32 ±2% for 10MHz < FOUT < 60MHz
k=1-4 ±1% for FOUT > 60MHz
m =1-64 long-term: 1% of FOUT or 100ps
n = 1-64 short-term: 50ps +1% of FOUT
There are two parameters of the PLL clock circuits that have significant impact
on possibility to extract randomness from the clock jitter, namely the output period
jitter of the PLL and range of frequency dividers. The level of timing jitter in clock
signals is for latest FPGAs families permanently decreased by FPGA vendors what
was proved also by our experimental measurements (described later). On the other
hand, the range of divisors in high-density devices is enlarged enough to achieve
wider range of synthesised clocking frequencies.
The jitter size is usually expressed in peak-to-peak value (what is a difference
between the smallest and the largest clock period) or 1-sigma value (σjit) (standard
deviation). Typical values of the period jitter depend on the technology and config-
uration of the PLL and can range from 3.5 ps to 10 ps for ASICs [22], or up to 100
ps for FPGAs [11, 19]. Since the technology of the embedded PLL and the quality
of the VCO is usually set by FPGA vendor, a user can modify the output jitter by
configuration of the PLL divider values (m, n, k) and loop filter bandwidth.
Jitter Generated in Altera Stratix FPGA In analog PLLs, various noise
sources cause that the PLL’s internal VCO fluctuates in frequency. Under ideal
conditions, the fluctuations visible as a jitter are caused only by analog (non-
deterministic) internal noise sources. In such case the noise is denoted as an intrinsic
jitter. Other possible frequency fluctuations are caused by variations of supply volt-
age, temperature, external interference through the power, ground, or by the internal
noisy environment generated by internal FPGA circuits [125]. The PLL’s control
circuitry adjusts the VCO back to the specified frequency and this change is seen
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