1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
plement the program code. The fully hardware solution needs greater logic resources
and eventually some data memory. In a mixed hardware-software design, parallel
and time critical operations can be done in a hardware (dedicated coprocessors)
and complex sequential and control operations in a software (main processor). In
our SOC design the speedup factor of the coprocessor application in relationship to
the entirely software-based solution can be measured quite easily: both implemen-
tations use the same embedded processor, Altera Nios soft core described further in
the following paragraph.
Embedded Nios Processor The Nios CPU [10] is a pipelined general-purpose
RISC processor that is generated by proprietary Altera VHDL generator (SOPC
Builder) and can be synthesised and embedded in all recent Altera FPGAs. The
Nios supports both 32-bit and 16-bit architectural variants. Both variants use 16-bit
instructions. The principal features of the Nios instruction set architecture are:
1. large, windowed register file,
2. simple, complete instruction set,
3. powerful addressing modes,
4. extensibility.
Existing Nios peripherals (e.g. UART, timer. . . ) as well as new custom peripherals
can be connected through an Avalon bus [9]. Avalon is a simple bus architecture
designed for connecting on-chip processor(s) and peripheral together into a SOC.
Comparison of Implementations The Nios processor is used as a control unit
in mixed implementations and as a main processor for the software implementa-
tion. The 32-bit version of the Nios CPU can optionally be configured to include
a hardware-supported integer multiplier. The additional logic is used by the MUL
instruction to compute 32-bit result in three clock cycles 1 . This option is not sup-
ported in the 16-bit Nios instruction set. In order to obtain realistic comparisons,
32-bit Nios CPU with hardware supported MUL instruction was used for software
implementation.
In order to compare them, we have implemented three different systems:
1 When using the MUL option with Altera Stratix devices, the hardware multiplier uses the
Stratix DSP blocks for implementation.
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