1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
from or writing to a single register in a specific ECM unit, the unit needs to be
recognised separately by unique address prefix. In combination with a address for
each unit, a register has a unique hardware address and can be addressed from
outside the ECM unit. This is imperative since the central control logic writes data
to these registers before phase 1 starts and it reads data from one of the registers
after phase 2 has been finished.
Each register can contain n bits and is organised in e = � �
n+1 words of size w
w
(see Figure 4 – 2). Memory access is performed word wise. Reasonable values for
w are w = 4, 8, 16, 32 what is given by the included multiplier requiring those word
widths.
0:
1:
e-1:
w bits
w bits
.
.
.
w bits
P1 register: e x w bits
. . . .
0:
1:
e-1:
w bits
w bits
.
.
.
w bits
P21 register: e x w bits
Figure 4 – 2 Organisation of the ECM unit’s memory registers for 21 variables with e words of
width w
The ALU performs the arithmetic modulo 2n, i.e., modular multiplication, mod-
ular squaring, modular addition and subtraction.
4.2.3 Choice of the Arithmetic Algorithms
The main purpose when we were designing the ECM was to synthesise an area-time
efficient implementation. All algorithms are chosen to allow achievement of a low
area and relatively high speed. Low area consumption can be achieved by structures,
which allow for a certain degree of pipeline and consequently do not require much
memory. For the ECM, we have chosen a set of algorithms which seem to be very well
suited for our purpose. The chosen algorithms are fully scalable and make possible
to analyse different unit parameters and their impact on units performance.
In the following, we briefly describe the algorithms for modular addition, subtrac-
tion, and multiplication to be implemented for the ALU. Squaring is done with the
multiplication circuit since a separate hardware circuit for squaring would increase
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