1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
1 Montgomery Modular Multiplication in Hard- ware
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FEI KEMT<br />
The Golić Design Golić’s goal is to provide digital TRNG built from logic gates<br />
only. Such design is cost effective and suitable for implementation on any digital<br />
chip. In article from Golić [70] the author proposes two new elements applied <strong>in</strong><br />
design of TRNG showed <strong>in</strong> Figures 5 – 4(a) and 5 – 4(b): the Galois r<strong>in</strong>g oscillator<br />
(GARO) and Fibonacci r<strong>in</strong>g oscillator (FIRO).<br />
(a) Galois r<strong>in</strong>g oscillator (b) Fibonacci r<strong>in</strong>g oscillator<br />
Figure 5 – 4 R<strong>in</strong>g oscillator structures proposed by Golić.<br />
Add<strong>in</strong>g more complex feedback loop <strong>in</strong> the r<strong>in</strong>g oscillator (RO) makes also its<br />
behaviour more complex and therefore more suitable for TRNG where the random-<br />
ness com<strong>in</strong>g from jitter spreads faster. In comparison to classical RO, the usage of<br />
GARO and FIRO yields a higher level of entropy and robustness of the generator.<br />
Additional entropy of the generator comes from frequent metastability effects <strong>in</strong> the<br />
sampl<strong>in</strong>g gate.<br />
In [44] Golić and Dichtl show results of practical implementation of TRNG us<strong>in</strong>g<br />
the oscillators presented above. The authors prove the randomness of the solution by<br />
analysis of the generator output after repeated restarts of the circuit. The standard<br />
deviation of the output signal voltage raises quickly after the restart and stabilises<br />
on significantly large level which assure randomness of the sample taken <strong>in</strong> this time<br />
period.<br />
The Kohlbrenner and Gaj Design The pr<strong>in</strong>ciple similar to PLL-based genera-<br />
tor [60] was proposed by Kohlbrenner and Gaj <strong>in</strong> [79]. Instead of PLL circuitry that<br />
is not present <strong>in</strong> all FPGAs, the authors use a pair of oscillator r<strong>in</strong>gs implemented<br />
<strong>in</strong> programmable logic area of FPGA. S<strong>in</strong>ce the pr<strong>in</strong>ciple expects a tight pair of<br />
frequencies generated by r<strong>in</strong>gs, the oscillators must be matched precisely. That re-<br />
quires also proper position<strong>in</strong>g of the r<strong>in</strong>gs <strong>in</strong>side the FPGA and manual corrections<br />
<strong>in</strong> placements and rout<strong>in</strong>g.<br />
The authors <strong>in</strong>vestigated also the <strong>in</strong>fluence of temperature on RO. The frequency<br />
of a RO tends to wander as the chip’s temperature varies. It is important to place<br />
the ROs <strong>in</strong> a pair close to each other so the difference between the frequencies is<br />
reduced due to m<strong>in</strong>imal difference <strong>in</strong> temperature.<br />
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