1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
frequency of the VCO is never constant and even by stable working conditions it
fluctuates around a mean value.
From the provided analysis we can conclude that PLL circuits are more suitable
for TRNG design based on jitter sampling as they offer a wide frequency range for
generated signals. Moreover, the internal PLL circuitry provide a reliable source of
a jitter.
Analog PLL in Altera and Actel FPGAs The core of clock circuitry embed-
ded in Altera and Actel FPGAs is formed by an analog PLL circuit surrounded
by several delay lines, clock multipliers/dividers, and circuits for interconnections
between internal clock network and external pads. Number of PLLs and their fea-
tures depend on chosen FPGA type and vendor. The Tables 6 – 1 and 6 – 2 present
the basic parameters of PLLs and clock circuits for FPGA devices from Altera
(APEX20K(E) [14], Cyclone [12,17] and Stratix [15,19]) and Actel (Axcelerator [2],
ProASICplus [3], ProASIC3(E) [4]).
Table 6 – 1 Parameters of PLL embedded in Altera FPGAs
family # of PLLs
dividers range
m n k
max. output period jitter
APEX20K 1 – – – 200ps
APEX20KE 2, 4 1-160 – * – 0.35% RMS of output period
Cyclone 1, 2 2-32 1-32 1-32 ±300ps for FOUT ≥ 100MHz
60mUI for FOUT < 100MHz
Cyclone II 2, 4 1-32 1-4 1-32 NA **
Stratix
Stratix II
* m/(n × k)=1-280.
4, 8×FPLL *** 1-32 1-32 1-32 ±100ps for FOUT > 200MHz
2, 4×EPLL 1-512 1-512 1-1024 ±20mUI for FOUT < 200MHz
4, 8×FPLL 1-32 1-4 1-32
2, 4×EPLL 1-32 1-32 1-32
NA **
** The jitter specification for the PLL output pins are dependent on the I/O pins in
its VCCIO bank, how many of them are switching outputs, how much they toggle,
and whether or not they use programmable current strength.
*** EPLL and FPLL stand for Enhanced and Fast PLL, respectively.
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