1 Montgomery Modular Multiplication in Hard- ware

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List of Tables 1 – 1 Comparison of the key length (in bits) for equivalent security level for public-key cryptosystems . . . . . . . . . . . . . . . . . . . . . . . 16 2 – 1 Address of operands from host processor level (LSB right) . . . . . . 33 2 – 2 PE sizes and speeds for old style Altera FPGAs . . . . . . . . . . . . 37 2 – 3 PE sizes and speeds for new style Altera FPGAs . . . . . . . . . . . . 37 2 – 4 Area occupation in number of LEs and maximal clock frequency (fclkMMM ) (MHz) of the MMM coprocessor (w = 32, n = 1..4) with MWR2MM CSA algorithm . . . . . . . . . . . . . . . . . . . . . . . . 38 2 – 5 Execution times of software implementation of MMM on Altera Nios development board (with APEX EP20K200 clocked at 50 MHz) . . . 40 2 – 6 Execution times of mixed hardware-software implementation of MMM on Altera Nios development board (with APEX EP20K200) for the CSA PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2 – 7 Execution times of mixed hardware-software implementation of the MMM on Altera Nios development board (with APEX EP20K200) for the CPA PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 – 1 Computational complexity and memory requirements for phase 2 de- pending on D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4 – 2 A command syntax for the ECM unit (LSB left) . . . . . . . . . . . . 59 4 – 3 Running Times of the ECM Implementation (198 bits modulus), p = 2, w = 32 (Xilinx Virtex2000E-6 and ARM7TDMI, 25MHz) . . . . . 67 6 – 1 Parameters of PLL embedded in Altera FPGAs . . . . . . . . . . . . 97 6 – 2 Parameters of PLL embedded in Actel FPGAs . . . . . . . . . . . . . 98 6 – 3 Parameters settings for different TRNG configurations . . . . . . . . 102 6 – 4 Configuration parameters of tested TRNG . . . . . . . . . . . . . . . 105 6 – 5 Results of quality evaluation of tested TRNG configurations . . . . . 105 6 – 6 Achievable sensitivity on jitter using two clock signals in Actel ProA- SICplus (FCLI = 40MHz) . . . . . . . . . . . . . . . . . . . . . . . . . 107 6 – 7 Area occupation of one PLL TRNG with delay line in FPGA Actel ProASICPlus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6 – 8 Mean values measured using the stochastic model E[pi] and the output sequence of the TRNG m = E [x(nTQ)] . . . . . . . . . . . . . . . 114 6 – 9 Results of statistical tests (FIPS) of TRNG output and number of random samples influenced by the jitter at different chip temperatures 118
List of Algorithms 1 – 1 Montgomery exponentiation algorithm [86], the definition of M ′ re- quires that gcd(M, R) = 1, b denotes base or radix. . . . . . . . . . . 10 1 – 2 The Montgomery modular multiplication algorithm for k-bit operands X = (xk−1, . . . , x1, x0), Y , and M . . . . . . . . . . . . . . . . . . . . 11 1 – 3 The basic radix-2 Montgomery multiplication algorithm for k-bit operands X = (xk−1, . . . , x1, x0), Y , and M . . . . . . . . . . . . . . . . . . . . 13 1 – 4 Optimized radix-2 Montgomery multiplication algorithm . . . . . . . 15 1 – 5 Key generation in ECC [78] . . . . . . . . . . . . . . . . . . . . . . . 18 1 – 6 Message signing in ECC [78] . . . . . . . . . . . . . . . . . . . . . . . 18 2 – 1 The multiple word radix-2 Montgomery multiplication MWR2MM CSA algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2 – 2 The multiple word radix-2 Montgomery multiplication MWR2MM CPA algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 – 1 Elliptic Curve Method . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3 – 2 Exponentiation for Curves in Montgomery Form . . . . . . . . . . . . 53 4 – 1 Modified MWR2MM algorithm . . . . . . . . . . . . . . . . . . . . . 62 4 – 2 Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4 – 3 Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Page 1 and 2: Technical University of Koˇsice Fa
Page 3 and 4: Metadata Sheet Author: Martin ˇ Si
Page 5 and 6: FEI KEMT ciel’ovej platformy a vl
Page 7 and 8: Acknowledgement There are several p
Page 9 and 10: Contents Introduction 1 1 Montgomer
Page 11 and 12: FEI KEMT 6.2.3 Analysis of TRNG in
Page 13: FEI KEMT 6 - 2 Block diagram of dig
Page 17 and 18: FEI KEMT π(p) prime counting funct
Page 19 and 20: FEI KEMT MWR2MM Multiple Word Radix
Page 21 and 22: FEI KEMT and Elliptic Curve Cryptog
Page 23 and 24: FEI KEMT The hardware implementatio
Page 25 and 26: FEI KEMT data inputs clock Look-up
Page 27 and 28: FEI KEMT A (X) request for B’s pr
Page 29 and 30: FEI KEMT Algorithm 1 - 1 Montgomery
Page 31 and 32: FEI KEMT In the Algorithm 1 - 1 the
Page 33 and 34: FEI KEMT by the radix b changes to
Page 35 and 36: FEI KEMT the ECC instead of the RSA
Page 37 and 38: FEI KEMT Algorithm 1 - 5 Key genera
Page 39 and 40: FEI KEMT 2 Montgomery Modular Multi
Page 41 and 42: FEI KEMT not significant. On the ot
Page 43 and 44: FEI KEMT Algorithm 2 - 2 The multip
Page 45 and 46: FEI KEMT Beside the internal struct
Page 47 and 48: FEI KEMT q x i S (j) 2 w-1 S (j) 1
Page 49 and 50: FEI KEMT x i x i-1 xi-n+1 Y (j) M (
Page 51 and 52: FEI KEMT especially if the access t
Page 53 and 54: FEI KEMT 2.2.3 Interface to Control
Page 55 and 56: FEI KEMT Clock Signal Distribution
Page 57 and 58: FEI KEMT 2.3.2 Montgomery Multiplic
Page 59 and 60: FEI KEMT 1. Fully software solution
Page 61 and 62: FEI KEMT 2.3.4 Implementation Resul
Page 63 and 64: FEI KEMT 3 Elliptic Curve Method in
Page 65 and 66:
FEI KEMT improving the area-time pr
Page 67 and 68:
FEI KEMT 3.3.1 Pollard’s (p − 1
Page 69 and 70:
FEI KEMT If the order of P ∈ E(Fq
Page 71 and 72:
FEI KEMT handicap of the Montgomery
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FEI KEMT Two major improvements hav
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FEI KEMT and case study with GNFS b
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FEI KEMT Table 4 - 1 Computational
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FEI KEMT from or writing to a singl
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FEI KEMT Algorithm 4 - 1 Modified M
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FEI KEMT Algorithm 4 - 2 Modular ad
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FEI KEMT microprocessor, e.g. Alter
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FEI KEMT timings of ECM implementat
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FEI KEMT hardware was implemented o
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FEI KEMT [68] what can be expressed
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FEI KEMT and a harvesting mechanism
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FEI KEMT control also all the syste
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FEI KEMT we can mention a generator
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FEI KEMT noise to binary signal a c
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FEI KEMT over time. For this reason
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FEI KEMT The Bucci and Luzzi Testab
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FEI KEMT CLI PLL PLL 1 2 CLJ CLK D
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FEI KEMT For R it holds that the in
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FEI KEMT extraction. In other words
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FEI KEMT and effort needed for repr
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FEI KEMT 6 True Random Number Gener
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FEI KEMT clock input F IN F FB Phas
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FEI KEMT Table 6 - 2 Parameters of
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FEI KEMT Since the size of the jitt
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FEI KEMT Table 6 - 3 Parameters set
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FEI KEMT where N1 is the number of
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FEI KEMT oscillator with frequency
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FEI KEMT Table 6 - 7 Area occupatio
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FEI KEMT 0,75 0,5 0,25 1 0 1 30 59
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FEI KEMT Stochastic Model The clock
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FEI KEMT Table 6 - 8 Mean values me
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FEI KEMT Figure 6 - 8 Sampled wavef
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FEI KEMT Table 6 - 9 Results of sta
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FEI KEMT Figure 6 - 11 Amount of sa
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FEI KEMT Figure 6 - 13 Amount of sa
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FEI KEMT 7 Research Contribution Wi
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FEI KEMT Curriculum vitae Professio
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FEI KEMT [16] Altera Corporation. S
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FEI KEMT [37] Bundesamt für Sicher
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FEI KEMT [54] Federal Information P
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FEI KEMT [71] Gura, N., Chang, S.,
Page 155 and 156:
FEI KEMT of Commerce, month = aug,
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FEI KEMT and C. Paar, Eds., no. 216
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FEI KEMT [128] Zimmermann, P. ECMNE
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