1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
clock
input
F IN
F FB
Phase
Detector
+/-
Delay
Line
clock
output
F OUT
Figure 6 – 2 Block diagram of digital DLL unit typical for Xilinx FPGA clock management
circuits
The DLL achieves very good results in delay compensation and clock condition-
ing. However, the available range of clock dividers is much more limited than in
case of PLL. It is possible to use an output pin with clock signal derived from input
signal, where its frequency may be doubled or divided by values: 1.5, 2, 2.5, 3, 4, 5,
8, or 16 in case of Spartan II FPGA devices [127].
6.1.1 PLL as Source of Randomness
Due to its digital nature the DLL in Xilinx devices is less sensible to noise envi-
ronment than analog PLL with VCO. The VCO tends to lock to frequencies of
disturbing external signals and therefore is required a use of separated networks for
power supply and ground connection mounted only to the clock circuitry. On the
other hand, the analog PLL makes possible a small area implementation providing
a wide range of clock frequencies. The DLL technology is limited in this direction
and offers only certain combinations of ratios between input and output frequencies.
Changes in the temperature or fluctuations of the supply voltage correlated to
switching activity of the closely placed logic may cause a drift in the generated
clock signal. As a compensation the loop makes adjustments of the delay elements
or VCO frequency what is recognised as a deterministic jitter added to the clock
signal. Other source of noise influencing the PLL circuitry is the input clock signal.
Therefore there is a tradeoff between compensation of the internal or external jitter.
All phase changes in the PLL or differences of delays in the DLL introduce a
jitter in the synthesised output signal. Filters inside the clock circuitry are matched
to eliminate the non-linearity caused by the loop and external influences, however
the intrinsic random noise of the VCO is always present in the output clock signal
and cannot be attenuated completely. Thanks to that, the PLL provides a promising
source of randomness suitable for an implementation of the TRNG. In addition, the
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