1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
Algorithm 4 – 1 Modified MWR2MM algorithm
1: S ⇐ 0
2: for i = 0 to n − 1 do
3: qi ⇐ xiY (0)
0
4: if qi = 1 then
+ S (0)
0
5: for j = 0 to e do
6: (Ca, S (j) ) ⇐ Ca + xiY (j) + M (j)
7: (Cb, S (j) ) ⇐ Cb + S (j)
8: S (j−1) ⇐ (S (j)
0 , S (j−1)
w−1..1)
9: end for
10: else
11: for j = 0 to e do
12: (Ca, S (j) ) ⇐ Ca + xiY (j)
13: (Cb, S (j) ) ⇐ Cb + S (j)
14: S (j−1) ⇐ (S (j)
0 , S (j−1)
w−1..1)
15: end for
16: end if
17: S (e) ⇐ 0
18: end for
rather than an addition (see Figure 4 – 3). All operations are done modulo 2n.
Algorithms 4 – 2 and 4 – 3 show the elementary steps of a modular addition and
subtraction, respectively.
If x + y ≥ 2n a reduction can be applied by simple subtraction of 2n. A variable
z contains the result and T is a (temporary) register. A comparison z < 2n takes
the same amount of time as a subtraction T = z − 2n. Thus, we compute the
subtraction in all cases and decide by the sign of the values, which one to take as
the result (z or T ). If T is the correct result, the content of T has to be copied to
the register z.
For a modular addition, we need at most
Tadd = 3(e + 1) (4.2)
clock cycles, where e is the number of words (for implemented non-redundant form
of operands e = � N+1
w
�
). On average, we would only have to reduce every second
time. However, since the control of phase 1 and phase 2 is parallelised for many
units, we have to assume the worst case running time which is given by Equation 4.2.
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