1 Montgomery Modular Multiplication in Hard- ware

Abstract in English
In the thesis we deal with two elementary blocks used in public key cryptosystems
– the first block is a modular multiplier for very long operands, the second one
is random number generator. Both blocks are designed on programmable target
platform (FPGA devices) what allows quick prototyping of proposed systems.
Our main goal in case of multiplier is to achieve a scalable and parametrised
solution, which is easily portable and adaptable according to a final target platform
and processed data. Note that due to requested high flexibility of solution the
achieved speed for clocking is lower than in case of dedicated design focused on speed.
On the other hand, our solution is perfect for prototyping and proof-of-concept
designs approach. In the thesis we analyse algorithm improvements in relation to
technical features of chosen FPGA families. Obtained universal arithmetic solution
needs to be enhanced with equally universal interface in order to connect a control
unit. As a result we obtained a building block – the multiplier for application in
cryptographic and cryptanalytic systems. For the multiplier it is possible to choose
a range of occupied physical area, computational time and size of operands.
The second area we deal with is a generation of random numbers in digital
environment of integrated circuits. A random number generator (RNG) is the only
cryptographic element for which there are no generally applied algorithms. The main
reason for this is in the fact that harvesting mechanism of RNG is tightly related to
a target platform. Physical sources of randomness are very limited in digital devices.
In addition, we deal with problematic issue of randomness testing. The chosen design
of RNG we analyse under changing temperature of a chip. Finally, the proposed
stochastic model of generator allows better understanding of its principle.
Abstract in Slovak
V dizertačnej práci sa zaoberáme dvoma elementárnymi blokmi pouˇzívan´ymi v
kryptografick´ych systémoch s verejn´ym kl’účom – prv´ym je násobička pre operácie s
vel’k´ymi číslami, druh´ym je generátor náhodn´ych čísel. Oba bloky sú realizované v
technológii hradlov´ych polí (obvody typu FPGA), čo umoˇzňuje vytvorenie prototypu
vo vel’mi krátkom čase.
Naˇsim hlavn´ym ciel’om v prípade násobičky je realizácia l’ahko parametrizova-
tel’ného a ˇskálovatel’ného rieˇsenia, ktoré umoˇzňuje prispôsobenie architektúry podl’a