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1 Montgomery Modular Multiplication in Hard- ware

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FEI KEMT<br />

Cryptographic primitives belong to group of systems suitable for reconfigurable<br />

devices due to the follow<strong>in</strong>g features:<br />

• standardized algorithms - most of the cryptographic algorithms, but random<br />

number generators are approved by <strong>in</strong>ternational standard organisations (e.g.<br />

[54–56,58,59]). Thus, the functionality described by mathematical algorithms<br />

and equations can by deeply studied and tailored to the hard<strong>ware</strong> structure. It<br />

is possible that group of secure cryptographic algorithms is changed <strong>in</strong> the time<br />

due to newly <strong>in</strong>vented attacks. The reconfigurable platform makes possible to<br />

remove obsolete algorithms from runn<strong>in</strong>g systems and provide the new ones,<br />

even without hard<strong>ware</strong> update or exchange.<br />

• several supported functionality modes and lengths of operands - while the num-<br />

ber of the most popular algorithms is limited, each of them provides a group of<br />

selectable parameters what results <strong>in</strong> need to implement a group of algorithms<br />

comb<strong>in</strong>ations.<br />

• sequential structure - <strong>in</strong> dependency on runn<strong>in</strong>g operation only selected crypto-<br />

graphic blocks need to programmed <strong>in</strong> a device and <strong>in</strong> case of operation change<br />

the other configuration is loaded. As an example we mentioned a scheme when<br />

at the beg<strong>in</strong>n<strong>in</strong>g of the communication a secret key is distributed to the parties<br />

by an asymmetric algorithm which is later misplaced by a faster symmetric<br />

encryption implemented on the same device.<br />

FPGA Architecture The underly<strong>in</strong>g FPGA architecture consists of an array of<br />

the smallest programmable units - logic elements (LE) or configurable logic blocks<br />

(CLB), and the programmable connection switches. A typical FPGA architecture<br />

consists of a high number (hundreds to thousands) of LEs and rout<strong>in</strong>g channels with<br />

different length/speed. By the LE we understand the smallest functional unit that<br />

is addressed by the mapp<strong>in</strong>g tools. Typically it consists of a look-up table (LUT)<br />

and a register (D flip-flop) (see Figure 1 – 1), what makes possible to implement the<br />

comb<strong>in</strong>atorial as well as sequential logic, or a small memory block. Additionally, the<br />

FPGA architecture may <strong>in</strong>clude special dedicated blocks or build<strong>in</strong>g items for other<br />

functions e.g. for stor<strong>in</strong>g data, comput<strong>in</strong>g multiplication and addition, synthesis<br />

clock signals. . .<br />

Modern FPGAs provide support for implementation of a wide range of the algo-<br />

rithms from area of signal process<strong>in</strong>g, communication or network<strong>in</strong>g. The crypto-<br />

5

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