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1 Montgomery Modular Multiplication in Hard- ware

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FEI KEMT<br />

6 True Random Number Generator<br />

The chapter is dedicated to analysis of jitter-based random generator under various<br />

aspects. Our work is based on the TRNG design proposed by Viktor Fischer and<br />

Miloˇs Drutarovsk´y published <strong>in</strong> 2002 [60]. We enhance the already published results<br />

summarised <strong>in</strong> the previous chapter. Our focus is put on analysis of the generator<br />

<strong>in</strong> chang<strong>in</strong>g work<strong>in</strong>g conditions and configurations sett<strong>in</strong>gs.<br />

Results of the research were published <strong>in</strong> the follow<strong>in</strong>g list of papers [47, 48, 61,<br />

62,114–116,119]. The ma<strong>in</strong> achievements of our research were done <strong>in</strong> the follow<strong>in</strong>g<br />

areas:<br />

• Analysis of PLL circuitry as a source of randomness – implementation issues,<br />

possible PLL configurations, verification of vendor parameters,<br />

• Analysis of TRNG implementation <strong>in</strong> different FPGAs – achievability study,<br />

design consideration, practical results,<br />

• Stochastic model of PLL-TRNG – proposal and practical verification,<br />

• Temperature <strong>in</strong>fluence on PLL-TRNG – practical attack on TRNG with results<br />

and suggestions for design.<br />

The chapter is structured as follows. In the Section 6.1 we describe two ways<br />

of clock synthesis <strong>in</strong> modern FPGAs and summarise the parameters of the clock<br />

circuitry verified by practical measurements of the PLL parameters. The Section 6.2<br />

provides an analysis of PLL configurations, practical results from Altera and Actel<br />

FPGA implementations of the generator and a stochastic model of the generator.<br />

In Section 6.3 we describe a non-<strong>in</strong>vasive attack on the generator together with<br />

practical outcomes. In the last part (Section 6.4) we discuss the obta<strong>in</strong>ed results<br />

and provide ideas on the further research.<br />

6.1 Clock Synthesis <strong>in</strong> FPGAs<br />

In present-day <strong>in</strong>tegrated digital systems, there is a need for numerous clock sig-<br />

nals with various frequencies. The synthesis of the clocks <strong>in</strong> separated circuits is<br />

not effective and the frequencies are too high to be generated by an external crys-<br />

tal. FPGA vendors offer for this purpose a clock circuitry embedded on the FPGA<br />

chip. Beside synthesis of clock signals with required frequencies it provides addi-<br />

tional functions mak<strong>in</strong>g possible a process<strong>in</strong>g of signals with very high frequencies.<br />

94

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