1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
1. Fully software solution implemented on a 32-bit Nios processor.
2. Mixed software-hardware design with 16-bit Nios processor and the pipelined
coprocessor including the CSA PE.
3. Mixed software-hardware design with 16-bit Nios processor and the pipelined
coprocessor including the CPA PE.
Further, we provide the details of each system design and comment the obtained
results.
1. The software implementation of the MMM algorithm has been written in the
Nios assembly language by using all known optimization techniques for the
target processor. The Separated Operand Scanning (SOS) MMM method [39]
was used as the best method for given Nios RISC architecture [66]. The
Table 2 – 5 shows the timings for the execution of the MMM on the fully
software solution running on the processor clocked at 50 MHz. The 32-bit
Nios processor occupies 2137 LEs without the logic for the integer multiplier
(for MUL instruction) that requires additional 446 LEs.
In case of the software implementation it is effective to apply a different algo-
rithms for the multiplication and squaring what reduces the execution time for
the squaring operation. However due to vulnerability against the side-channel
attacks it is better to align the execution times of both operations.
Table 2 – 5 Execution times of software implementation of MMM on Altera Nios development
board (with APEX EP20K200 clocked at 50 MHz)
Length Method Multiplication Squaring
(e × w) (ms) (ms)
1024 SOS32MEM 2.40 1.87
2048 SOS32MEM 9.47 7.24
2. In the mixed hardware-software design the multiplication and squaring is com-
pletely implemented in the hardware. Both operations share the same arith-
metic unit. Due to move of the computational complexity from the main pro-
cessor to the dedicated coprocessor one does not need to use the 32-bit version
of the Nios core. Instead of the 32-bit controller one can include the 16-bit
40