1 Montgomery Modular Multiplication in Hard- ware

FEI KEMT
In the coprocessor we need to store four operands for the MMM computations:
three input operands X, Y, M and the result S. The storage of S requires one or
two registers for a case of the non-redundant or redundant representation form,
respectively. The scalability feature applied to the ALU needs to be adopted to the
memory block, too.
The requirements for the scalable design make possible that the architecture
is easily adaptable to the length of operands different from the one for which the
system was originally designed. In the memory block the number of stored variables
is constant (four or five, depending on the chosen implementation). What varies is
the number of words and consequently the number of bits needed to address them.
We propose a model in which the each word of every variable can be addressed
as from the coprocessor as well as from the host unit. We recognise an internal
address of a word that specifies its location in given coprocessor and register, a
register address that makes possible to choose a register with required variable
and finally a coprocessor address distinguishing between several ALUs. With this
memory management a control unit can address any word of a chosen coprocessor,
store there the input values for computations and afterwards read the results for
further processing. Number of address bits for each level can be adopted according
to number of coprocessors, variables and number of words. The address width is
usually given by the word width of the interface between the processor and the
coprocessor. For the address longer than the interface word width an appropriate
address model needs to be chosen - accepting several address signals in parallel or
differencing the address type in other way.
Table 2 – 1 Address of operands from host processor level (LSB right)
coprocessor register internal
XX XXX XXXXXXX
The memory address bits are assigned as shown in Table 2 – 1 (LSB is right).
The CPU in the presented example of the address format can handle up to 4 MMM
coprocessors (two bits address) with 8 operands (three bits address) each composed
of 128 words. Such configuration is suitable for the RSA computations on the
operands’ length n = 2048 bits and word width w = 16 bits what gives e = 128
number of words.
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