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NP Control with Carrier based PWM 103 5.2.3 Performance evaluation For the performance analysis of the controllers, a NP voltage reference step has been simulated. The Maximum dv/dt achieved is proportional to the maximum average NP current and is a measure for NP control capacity and thus the performance of the control scheme. TABLE 36, OPERATING POINT FOR THE SIMULATIONS IN TABLE 37 TO TABLE 38 m f out U DC U FC R load L load ϕ UI C DC C FC f sw 0.6 50 Hz 240 V 60 V 0.5 Ω 14.2 mH 1.53 990µF 1120µF 2000 Hz All simulations in this paragraph are based on balanced undistorted systems. The controller gain in the simulations has been chosen such that the controllers saturate at high voltage deviation in the NP, but have a low impact close to the set point. The dv/dt obtained with the real time NP current function is 800V/s (20V / 25ms in the graph). With an effective capacitance of 4mF (upper and lower DC link capacitors in parallel), we get a NP current of 3.2A during the transient corresponding with 18% of the peak phase current of 18A. The 6 th harmonic injection has a dv/dt of 600 V/s resulting in an NP current of 2.4A, which corresponds with 13% of the peak phase current. This is a very good match with the values obtained by calculation and shown in Figure 68. The two schemes provide very similar currents during transients and the new set point is reached after around 50ms. The phase output voltages in TABLE 37 show fundamentally different behavior for the two schemes: The 6 th harmonic injection scheme has moderate 3 rd harmonic in steady state; during transient operation, the 6 th harmonic is clearly visible. The real time NP current function scheme applies a very high 3 rd harmonic content in steady states, which minimizes the NP current ripple; in transient operation, a constrained DC is injected rather than a 6 th harmonic. The 6 th harmonic injection scheme results in a higher NP voltage ripple but yields smoother phase voltage waveforms. Note that this results depends largely on the choice of underlying modulation scheme and the controller gain. The proposed modulation schemes keep the differential voltage and the resulting output currents undistorted. There is a difference in the switching frequency on the device level (at a given apparent output switching frequency) and the resulting losses. However the impact is relatively low in the given operating point. The steady state switching losses can be reduced by only 2% through the use of the 6 th harmonic injection scheme. Experimental results comparing the NP control performance of these schemes with the more powerful virtual vectors are given in paragraph 7.4.
104 NP Control with Carrier based PWM TABLE 37, NP VOLTAGE REFERENCE STEP RESPONSE, M = 0.6, ϕ = 1.53, SIMULATION 6 th harmonic injection Real time NP current function Flying capacitor voltage (V) Phase output voltage (V) NP voltage (V) 6th harmonic injection DC CM injection Phase current (I) fswitch 2149 Hz (output) 2249 Hz (device) 2137 Hz (output) 2323 Hz (device) Note the different time scales The real time NP current functions have been recorded over time in those simulations.
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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ML Converter Topologies 13 3 ML CON
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ML Converter Topologies 15 The four
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ML Converter Topologies 17 Each swi
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ML Converter Topologies 19 size doe
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ML Converter Topologies 21 plus (a)
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ML Converter Topologies 23 N >= 2,
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ML Converter Topologies 25 (a) (b)
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ML Converter Topologies 27 (a) (b)
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ML Converter Topologies 29 In a pra
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ML Converter Topologies 31 reality,
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ML Converter Topologies 33 All cons
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ML Converter Topologies 35 TABLE 16
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ML Converter Topologies 37 TABLE 17
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ML Converter Topologies 39 3.7.4.1
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ML Converter Topologies 41 f C sw =
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ML Converter Topologies 43 A second
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ML Converter Topologies 45 Limitati
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ML Converter Topologies 47 1 K M 2
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ML Converter Topologies 49 3.8 Exec
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Application and Verification 161 TA
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Application and Verification 165 TA
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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