Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

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NP Control with Carrier based PWM 119 Figure 80 shows the complete state machine for three SMC modulation types. The states are numbered such that each bit corresponds with the state of an individual cell {c11 c12 c21 c22}. Any generic PWM modulator can be used for the determination of the output levels of the individual phases. 5.3.4 Experimental verification For the experimental verification, 5-level SMC (operated at 100V, 15A) has been used. The prototype features current sensors in the neutral point to observe and / or control the NP currents and voltages. One phase leg is shown in Figure 81. Figure 81, SMC phase leg (7-level, operated as 5-L) 5.3.4.1 Verification of NP currents The NP current measurement is based on an H-bridge configuration to verify the NP currents in any given operating point (random voltage and current). One half bridge is operating as a voltage source in open loop. The other half bridge is controlling the current in the load (R-L load) in closed loop with a PID controller. Experimental results for the NP current are shown in Figure 82. The operating point is chosen at α L=0.625. The NP current either corresponds with the output current or remains at zero. (a) (b) (c) Figure 82, Measured data: standard type (left), type A (middle) and type B (right), Ch1 (blue): phase current, Ch2 (red): NP current, Ch3 (green): output voltage The NP currents in the whole operating range of the converter has been verified by measuring the NP current in selected operating points (Figure 83).
120 NP Control with Carrier based PWM Figure 83, Calculated and measured NP currents in selected operating points (p.u. values) There is a good match between experiment and theoretical characteristics. 5.3.4.2 Verification of NP control scheme NP voltage control has been implemented with a hysteresis controller as presented in the previous chapter. A R-L load has been connected to the 3 phase SMC converter. The NP is not connected to any external source but is only controlled by the converter itself in this case. state 5 state 4 state 3 (a) (b) Figure 84, Measured data: NP control (left: 40ms/div, right: zoom with 2ms/div), m = 0.8, Ch1 (blue): NP voltage, Ch2 (red): state, Ch3 (green): NP current, Ch4 (purple): phase voltage Figure 84 shows the NP control in operation. An unbalance current in the DC link leads to a voltage rise during the time with standard modulation. Note that the difference in NP current is only visible in the indicated areas, as the modulation types only differ in the middle output voltage regions. Figure shows a similar case with reduced modulation index. The difference in NP current is clearly visible for the three half waves (three different modulation types) in the plot. The DC link unbalance is generated with a static CM offset in this case (ca. 10% V DC), which is visible in the phase output voltage. The control method with modulation type can be combined with CM voltage variation without problems. This can either be used to improve NP control by using CM and modulation type variation together, or it can be used to introduce a CM voltage independently of the NP control (either for harmonic optimization or for CM voltage reduction on the motor for a reduction of the bearing currents).
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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x Résumé français (French summar
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xii Résumé français (French summ
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xiv Résumé français (French summ
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xvi Résumé français (French summ
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xviii Résumé français (French su
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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ML Converter Topologies 13 3 ML CON
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ML Converter Topologies 15 The four
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ML Converter Topologies 17 Each swi
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ML Converter Topologies 19 size doe
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ML Converter Topologies 21 plus (a)
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ML Converter Topologies 23 N >= 2,
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ML Converter Topologies 25 (a) (b)
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ML Converter Topologies 27 (a) (b)
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ML Converter Topologies 29 In a pra
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ML Converter Topologies 31 reality,
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ML Converter Topologies 33 All cons
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ML Converter Topologies 35 TABLE 16
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ML Converter Topologies 37 TABLE 17
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ML Converter Topologies 39 3.7.4.1
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ML Converter Topologies 41 f C sw =
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ML Converter Topologies 43 A second
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ML Converter Topologies 45 Limitati
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ML Converter Topologies 47 1 K M 2
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ML Converter Topologies 49 3.8 Exec
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52 3-L DC Link ML Converter Propert
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

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