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NP Control with Carrier based PWM 111 Essentially, there are 4 new types of states indicated with type 3 in TABLE 43. All others correspond with the states of the type 1, type 2 converters or are available in all ML ANPC converters. Two of these extra states generate a zero output (neutral point output) without generating a NP current. These states alone cannot balance the FC voltages, so that they need to be combined with the other remaining new states as indicated in Figure 70. 1 2 3 4 1 2 Figure 70, ANPC type 3 with type 3 zero voltage output states, coloring corresponds with TABLE 43 The resulting NP current for NP voltage output is ½ as can be seen from the table in Figure 71 (b). This corresponds with the NP current generated for –U DC/4 and +U DC/4. It can be expected that a proper modulation schemes making a linear combination of the required states will yield a constant NP current of ½ for V out from –U DC/4 to +U DC/4. Outside of that range, there are no type 3 states available and the standard NP current function applies (see Figure 72 b). 5.3.1.1 Design of a suitable modulation scheme The following modulation schemes apply single commutations between adjacent states only and make use of the available redundant states. The carrier based PWM applies phase shifted carriers for the 4 cells. There are 6 different sequences possible; always two of them are equivalent as the sequence is simply reversed. The 3 fundamentally different sequences are shown in Figure 71. A current is flowing in the NP if the first cell of either stage 1 or stage 2 and the first cell of stage 3 are in different states. This corresponds with regions enclosed by carrier 1 and carrier 3 in Figure 71. Obviously, this region is larger in the case of a large phase shift and smaller for the case of a small phase shift, which is reflected in the average NP currents. Not all possible carrier sequences lead to a balanced operation. Sequence {C 1C 4C 2C 3} applies type 3 zero outputs and results in all balanced flying capacitors. Sequence {C 1C 2C 3C 4} and sequence {C 1C 2C 4C 3} use type 3 and standard zero outputs and generate unbalance in the flying capacitors. All capacitors will be balanced if the two types of sequences are combined, resulting in a long sequence {C 1C 2C 3C 4C 1C 2C 4C 3}.
112 NP Control with Carrier based PWM Carrier 1 Carrier 2 Carrier 3 Carrier 4 Area where a neutral point current is flowing (a) Carrier sequence {C 1C 2C 3C 4}, NP status sequence {9-12-6-3} DSx Cells status INP IFC1 IFC2 IFC3 9 (1001) 1 0 + - 12(1100) 1 0 0 0 6 (0110) 1 - 0 + 3 (0011) 1 0 0 0 Average 1 - + 0 (b) Carrier sequence {C 1C 4C 2C 3}, NP status sequence {9-10-6-5} DSx Cells status INP IFC1 IFC2 IFC3 9 (1001) 1 0 + - 10(1010) 0 + 0 + 6 (0110) 1 - 0 + 5 (0101) 0 0 - - Average ½ 0 0 0 (c) Carrier sequence {C 1C 2C 4C 3}, NP status sequence {3-10-12-5} DSx Cells status INP IFC1 IFC2 IFC3 3 (0011) 1 0 0 0 10(1010) 0 + 0 + 12(1100) 1 0 0 0 5 (0101) 0 0 - - Average ½ + - 0 (d) Long NP status sequence {9-12-6-3-5-12-10-3} DSx {1100}BSx {0110}BSx {0011}BSx {0101}BSx {1100}BSx {1010}BSx {0011}BSx {1001}BSx {1100}BSx {0110}BSx Figure 71, Carrier based PWM commutation schemes for the ANPC type 3
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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x Résumé français (French summar
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xii Résumé français (French summ
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xiv Résumé français (French summ
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xvi Résumé français (French summ
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xviii Résumé français (French su
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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ML Converter Topologies 13 3 ML CON
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ML Converter Topologies 15 The four
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ML Converter Topologies 17 Each swi
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ML Converter Topologies 19 size doe
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ML Converter Topologies 21 plus (a)
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ML Converter Topologies 23 N >= 2,
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ML Converter Topologies 25 (a) (b)
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ML Converter Topologies 27 (a) (b)
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ML Converter Topologies 29 In a pra
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ML Converter Topologies 31 reality,
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ML Converter Topologies 33 All cons
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ML Converter Topologies 35 TABLE 16
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ML Converter Topologies 37 TABLE 17
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ML Converter Topologies 39 3.7.4.1
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ML Converter Topologies 41 f C sw =
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ML Converter Topologies 43 A second
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ML Converter Topologies 45 Limitati
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ML Converter Topologies 47 1 K M 2
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ML Converter Topologies 49 3.8 Exec
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52 3-L DC Link ML Converter Propert
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Page 81 and 82: 60 3-L DC Link ML Converter Propert
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Page 144 and 145: NP Control with Optimal Sequence SV
Page 170 and 171: Application and Verification 149 7
Page 172 and 173: Application and Verification 151 TA
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Application and Verification 161 TA
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Application and Verification 163 7.
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Application and Verification 165 TA
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Application and Verification 167 7.
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

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