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Christoph Haederli - Les thèses en ligne de l'INP - Institut National ...

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NP Control with Optimal Sequ<strong>en</strong>ce SVM 145<br />

The algorithm takes time to compute; the resulting <strong>de</strong>lay <strong>de</strong>gra<strong>de</strong>s performance and limits the<br />

control bandwidth. Comparing the differ<strong>en</strong>t modulation types we can state:<br />

- Standard carrier based PWM or a NTV SVM can be done with very little<br />

computational effort.<br />

- Optimal sequ<strong>en</strong>ce SVM required significant calculation time<br />

o Around 2500 floating point operations are required in each modulation cycle<br />

in the single commutation scheme<br />

o Around 50’000 floating point operations are required in each modulation<br />

cycle in the double commutation scheme.<br />

The maximum calculation time allowed <strong>de</strong>p<strong>en</strong>ds highly on the switching frequ<strong>en</strong>cy and the<br />

control bandwidth required. A maximum calculation time of around 100µs is assumed to yield<br />

reasonable performance in standard applications. This seems possible for single commutation<br />

optimal sequ<strong>en</strong>ce SVM (either in an optimized C routine or hard programmed in an FPGA). A fast<br />

<strong>en</strong>ough implem<strong>en</strong>tation of the optimal sequ<strong>en</strong>ce SVM with double commutations is a very big<br />

chall<strong>en</strong>ge with today’s available control hardware, but it may be feasible in the not too distant<br />

future.<br />

6.2.3 Implem<strong>en</strong>tation on control platform and experim<strong>en</strong>tal verification<br />

The predictive optimal sequ<strong>en</strong>ce SVM has be<strong>en</strong> implem<strong>en</strong>ted on a commercial control<br />

platform (OPCoDe by ABB), which allows implem<strong>en</strong>tation of control in Matlab / Simulink,<br />

simulation of the co<strong>de</strong> in that <strong>en</strong>vironm<strong>en</strong>t and direct downloading of the same co<strong>de</strong> to the target<br />

application. In or<strong>de</strong>r to allow implem<strong>en</strong>tation on the CPU rather than on the FPGA, the co<strong>de</strong> has<br />

be<strong>en</strong> optimized for fast execution.<br />

6.2.3.1 Modulator adaptations for implem<strong>en</strong>tation on control platform<br />

The sequ<strong>en</strong>ce l<strong>en</strong>gth has be<strong>en</strong> reduced to 3 and only single commutations are allowed. This<br />

reduced the maximum number of sequ<strong>en</strong>ces to be calculated to 40 (5 starting states with 2 trees<br />

each, each of the trees having 4 sequ<strong>en</strong>ces). THD calculation has be<strong>en</strong> exclu<strong>de</strong>d to further speed up<br />

calculation. No additional optimal states are consi<strong>de</strong>red.<br />

6.2.3.2 Experim<strong>en</strong>tal results<br />

The optimal sequ<strong>en</strong>ce SVM algorithm has be<strong>en</strong> verified on the 6kVA 5-L ANPC prototype.<br />

Figure 101 shows one specific operating point of m = 0.9. The DC-si<strong>de</strong> of the converter is supplied<br />

by a constant DC source of V DC = 80V and the AC-si<strong>de</strong> terminals are connected to a three-phase<br />

RL load (10 Ω and 4.2 mH, cos(ϕ) = 0.966 at 25 Hz). The resulting curr<strong>en</strong>t is 2.8 A.

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