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ML Converter Topologies 27 (a) (b) (c) (d) (e) Figure 31, Novel 5-L ANPC variations with different flying cap arrangement The current paths and switching states for these topologies are not listed here for the sake of brevity. However, they can be anticipated by comparing Figure 30 and Figure 31; Figure 33 illustrates a subset of converter states for Figure 31 (a). Note that a switch in common path for upper MC operation and lower MC operation can always be replaced by two parallel or quasi parallel paths. For example the circuit in Figure 31 (d) can be transformed into the circuit in Figure 32, now featuring three distinct current paths (SMC type) with a more balanced loading of the switches than the circuit in Figure 31 (d). More ways of implementation are obviously possible (exchanging capacitor positioning in upper and lower DC link, exchanging NPC stage with SMC stage, etc.). Figure 32, Novel 5-L topology with direct path from NP to output All these concepts can also be extended to higher level converters, leading to a very vast number of different circuits. Most of them are not really attractive for industrial implementation, as they may be asymmetrical, feature a lot of different commutation loops to be designed and may have highly unbalanced losses. The topologies in Figure 31 (a) and (b) are notable exceptions as they are symmetrical.
28 ML Converter Topologies 3.6.1 Operation of the ANPC 1 variation with backward half bridge The topology in Figure 31 (a) has a special feature making it interesting for implementation: The transition from upper to lower DC link and vice versa does not have to be done with a 2 level commutation as in the ANPC 1 but can be done with a commutation in the half bridge on the flying capacitor facing the DC link. This results in a very smooth glitch free operation of the converter (as is also the case for the SMC). (a) (b) (c) (d) (e) Figure 33, Commutations for the ANPC 1 variation with backward half bridge A transition from level 0 (minimum output voltage) to level 4 (maximum output voltage) is shown in Figure 33. The commutation from (a), level 0 to (b), level 1 is a standard half bridge commutation of the output cell. The transition from (b), level 1 to (c), level 2 is between one of the switches connecting to the NP and any of the three switches connected to the lower DC link. Only one of the lower three switches is required for blocking during operation of the lower MC converter. The other two switches (indicated by the dotted green line in (c)) may stay on or also turn off. The active switch used may also alter, so that the switching losses are distributed among the three devices. The transition from (c), level 2 to (d), level 3 is the transition changing from lower MC operation to upper MC operation. The commutation is done with the backward oriented half bridge connected to the flying capacitor. This commutation is straight forward and can be done independently of current direction or level. Care must be taken with the outer switches. The following sequence must be used to not apply high voltage on any individual switch: 1. turn off all switches in outer paths (if not already off) 2. turn off conducting switch in backward oriented half bridge 3. turn on blocking switch in backward oriented half bridge 4. optionally turn on two of the outer switches connecting to the DC link (on the new active side of the DC link) The additional transition of the outer switches does not create any losses as the load current is flowing in the middle path and there is no current in the outer paths connecting to the DC link.
Page 1 and 2: THÈSE En vue de l'obtention du DOC
Page 3: Acknowledgements i ACKNOWLEDGEMENTS
Page 6 and 7: iv Table of Contents 3.4 Generic ML
Page 8 and 9: vi Table of Contents 7.1 General mo
Page 10 and 11: viii Résumé français (French sum
Page 12 and 13: x Résumé français (French summar
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Page 16 and 17: xiv Résumé français (French summ
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Page 22 and 23: Introduction 1 2 INTRODUCTION This
Page 24 and 25: Introduction 3 tighter capacitor di
Page 26 and 27: Introduction 5 TABLE 1, OPERATING R
Page 28 and 29: Introduction 7 2.3 Glossary Note th
Page 30 and 31: Introduction 9 2.4 Nomenclature Not
Page 32 and 33: Introduction 11 DPC DSP DTC FC FPGA
Page 34 and 35: ML Converter Topologies 13 3 ML CON
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Page 46 and 47: ML Converter Topologies 25 (a) (b)
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Page 58 and 59: ML Converter Topologies 37 TABLE 17
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NP Control with Carrier based PWM 8
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Application and Verification 149 7
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Application and Verification 155 7.
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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