Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

More documents

Recommendations

Info

3-L DC Link ML Converter Properties 51 4 3-L DC LINK ML CONVERTER PROPERTIES This chapter explores the properties of 3-L DC link ML converters (SMC, ANPC, as introduced in the previous chapter) points out their limitations according to state of the art operation. The capacitor voltage control is a key aspect when applying those topologies. The flying capacitors can usually be controlled by the application of redundant states. Therefore, the main focus of the following investigations is on the controllability of the NP current. The two most powerful approaches for modifying the NP current are CM injection and use of redundant states. Consequently, there is a strong focus of this thesis on those two items. Other approaches have been proposed in literature (generation of output current harmonics, use of auxiliary circuits like break chopper) but are not investigated in depth in this thesis. 4.1 General converter properties All 3-L DC link ML converters have some common properties as illustrated in Figure 44. There is a split DC link with the three supply potentials DC-, NP and DC+. The output current of one phase leg is supplied by any of these three potentials with some intermediate circuit that may contain switches and capacitors. The NP may be supplied by capacitors only or it may be connected to a separate supply. In case of a separate supply, there is no need for control of that potential. This thesis considers the case with supply for DC+ and DC- only, without separate supply for the NP. In this case, the potential in the NP needs to be balanced, either passively or actively. DC+ DC+ U DC NP U out U DC NP U out DC- DC- (a) (b) Figure 44, 3-L DC link converters, (a) general case, (b) triangle case The very general case indicated in Figure 44 (a) includes hybrid converters as shown in Figure 29 (c). The analysis in this thesis is limited to the more constrained topology according to Figure 44
52 3-L DC Link ML Converter Properties (b): all converters have series connected unipolar switches connecting the DC link directly to the output, and forming a generic triangle. The output voltage is thus constrained to within the DC link potential. No boosting is possible. Multiple flying capacitors can be integrated in a switch circuit within the triangle formed by the outer switches. The required blocking voltage in any switch position is indicated by the number of series connected devices in the generic representation. However, this doesn’t necessarily mean commutation takes place with the according voltage. In the SMC for example, the outer switches need to block twice the voltage of an inner switch, but they only need to actively commutate a single level voltage. Double the blocking voltage is only required, as the output voltage may be pulled to the other rail by the opposite MC converter branch. The most important representatives of this family of converters are the previously introduced (A) NPC, the ML-ANPC, and the SMC shown in Figure 25 and Figure 26. The new topologies according to Figure 31 and Figure 32 also belong to that family and have similar properties as the ANPC 2. Operating principles according to the state of the art are described in this chapter. More sophisticated approaches are presented in the following chapters on new control and modulation schemes. 4.1.1 Some definitions For the analysis of the converter properties, PWM is used (carrier based or SVM) and only optimal modulation is considered, applying only single level steps in the output. Average values are used for the description of the NP current. The impact of the current ripple is not considered. This can be done if the switching frequency is significantly higher than the fundamental frequency. Based on those assumptions, we can state the following: - All currents in the system can be describes in function of load currents and duty cycles (α) of the commutation cells. The following examples with the basic commutation cells illustrate the relationship between currents and duty cycles. S1 U DC S2 I out U out Z load Figure 45, Half bridge with load t = T t T t t (30) S1 _ on MP − S1 _ off = MP − S 2 _ on = t = d1 = 1 − d = S 2 _ off S1_ on α 2 (31) TMP
Page 1 and 2:
THÈSE En vue de l'obtention du DOC
Page 3:
Acknowledgements i ACKNOWLEDGEMENTS
Page 6 and 7:
iv Table of Contents 3.4 Generic ML
Page 8 and 9:
vi Table of Contents 7.1 General mo
Page 10 and 11:
viii Résumé français (French sum
Page 12 and 13:
x Résumé français (French summar
Page 14 and 15:
xii Résumé français (French summ
Page 16 and 17:
xiv Résumé français (French summ
Page 18 and 19:
xvi Résumé français (French summ
Page 20 and 21: xviii Résumé français (French su
Page 22 and 23: Introduction 1 2 INTRODUCTION This
Page 24 and 25: Introduction 3 tighter capacitor di
Page 26 and 27: Introduction 5 TABLE 1, OPERATING R
Page 28 and 29: Introduction 7 2.3 Glossary Note th
Page 30 and 31: Introduction 9 2.4 Nomenclature Not
Page 32 and 33: Introduction 11 DPC DSP DTC FC FPGA
Page 34 and 35: ML Converter Topologies 13 3 ML CON
Page 36 and 37: ML Converter Topologies 15 The four
Page 38 and 39: ML Converter Topologies 17 Each swi
Page 40 and 41: ML Converter Topologies 19 size doe
Page 42 and 43: ML Converter Topologies 21 plus (a)
Page 44 and 45: ML Converter Topologies 23 N >= 2,
Page 46 and 47: ML Converter Topologies 25 (a) (b)
Page 48 and 49: ML Converter Topologies 27 (a) (b)
Page 50 and 51: ML Converter Topologies 29 In a pra
Page 52 and 53: ML Converter Topologies 31 reality,
Page 54 and 55: ML Converter Topologies 33 All cons
Page 56 and 57: ML Converter Topologies 35 TABLE 16
Page 58 and 59: ML Converter Topologies 37 TABLE 17
Page 60 and 61: ML Converter Topologies 39 3.7.4.1
Page 62 and 63: ML Converter Topologies 41 f C sw =
Page 64 and 65: ML Converter Topologies 43 A second
Page 66 and 67: ML Converter Topologies 45 Limitati
Page 68 and 69: ML Converter Topologies 47 1 K M 2
Page 70: ML Converter Topologies 49 3.8 Exec
Page 75 and 76: 54 3-L DC Link ML Converter Propert
Page 110 and 111: NP Control with Carrier based PWM 8
Page 122 and 123:
NP Control with Carrier based PWM 1
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
NP Control with Optimal Sequence SV
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Application and Verification 149 7
Page 172 and 173:
Application and Verification 151 TA
Page 174 and 175:
Application and Verification 153 Th
Page 176 and 177:
Application and Verification 155 7.
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188:
Page 191 and 192:
170 Conclusions and Outlook 8.1.2 M
Page 193 and 194:
172 Conclusions and Outlook 8.2 Out
Page 195 and 196:
174 Conclusions and Outlook 8.3 Sum
Page 197 and 198:
176 Appendix I = 1− ) (99) ( C 2
Page 199 and 200:
178 Appendix TABLE 78, FLYING CAPAC
Page 201 and 202:
180 Appendix 9.3 Single phase NP cu
Page 203 and 204:
182 Appendix 9.4 States of the ANPC
Page 205 and 206:
184 Appendix 9.5 NP currents as a f
Page 207 and 208:
186 Appendix 9.5.3 Maximum and mini
Page 209 and 210:
188 Appendix 9.6 NP current functio
Page 211 and 212:
190 Appendix TABLE 91, NP CURRENT I
Page 213 and 214:
192 Appendix TABLE 93, NP CURRENT I
Page 216 and 217:
Bibliography 195 10 BIBLIOGRAPHY [1
Page 218 and 219:
Bibliography 197 [33] P. Steimer,
Page 220 and 221:
Bibliography 199 neutral point bala
Page 222 and 223:
Bibliography 201 [88] J. Pou, J. Za
show all

Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

Create successful ePaper yourself

Delete template?

Save as template?