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ML Converter Topologies 35 TABLE 16, MAXIMUM NUMBER OF PARALLEL CURRENT PATHS AND PARALLEL CURRENT PATH RATIO MLDC MC SMC Note 1 ANPC 1 SCx+FCx ANPC 2 FCx+SCx ANPC 3 FCx+FCx FSx+FCx FC2 * x M 2 LC Max. number of paths 2*N (diodes) 2 3 4 4 4 2*N N 4 Max. divided by Min. number of paths N 1 1 (full) 1.5 (NPC output) 2 2 2 N N/2 1 (full) 2 (shared) output cell) Note 1: including the ANPC variations in Figure 31 (c) – (e) and Figure 32 The MC provides the most favorable configuration regarding parallel paths and resulting loss distribution. MC converter and cascaded H-bridge converter have inherently balanced losses in all devices; all others have differing current distribution at low and high modulation depth. Also active schemes cannot fully balance the resulting losses. The SMC and its variations also provide a low number of maximum parallel paths and allows for designs with a constant number of paths. All ANPC variations have a higher maximum path number and always include sections with different path numbers. However, the maximum number of paths is constant and does not scale with N as for some other topologies. In addition, the strategies proposed above provide reasonable switch usage by proper balancing of the losses. The M 2 LC provides a constant number of parallel paths in all sections; on the other hand, the total number of switches is high. 3.7.2.1 Total semiconductor losses Overall semiconductor losses are very similar in all of the presented topologies for a given average device switching frequency. This can be stated without detailed calculation based on the following two assumptions: 1. The current path is always through N switching devices (as there are N sections, see Figure 23), either active switch or diode, independently of topology. The share between IGBT and diode may vary slightly, but will have no significant impact on the overall conduction losses. All topologies perform very similar in that respect, unless a different switch dimensioning (silicon area) is used. 2. A change of one output level involves a commutation from one IGBT to one diode or vice versa for all topologies. A given output voltage waveform defines the number of commutations for all topologies, resulting in similar overall switching losses for all topologies. Nevertheless, the considered topologies may vary a lot regarding loss distribution (as presented above) and the total switching losses: The design of different topologies may not be optimized for the same average switching frequency. To minimize capacitance, all cells generating single level steps should be operated at high frequency, whereas cells generating multiple level steps should be operated at low frequency. This means that topologies with a large number of high frequency switching cells are likely to generate higher losses. E.g. the ANPC 3 will generate more losses than
36 ML Converter Topologies the ANPC 1 if capacitor energy is minimized, and the ANPC 3 will thus generate a high apparent output switching frequency and require less filtering and generate lower filter losses. The degree of freedom in dimensioning components and choosing modulation schemes (with or without loss balancing scheme) is very high. A comparison of the considered topologies regarding losses is therefore only meaningful if a set of constraints based on a given application is given. As the approach in this chapter is very generic and meant for a wide variety of applications, such a comparison is not done here. A good comparison based on real converter dimensioning can be found in [32] for a number of topologies. 3.7.3 Modularity and Scalability Modularity can be defined on different levels and in different dimensions. In the context of this topology comparison, the modularity of interest is on the main circuit level. For simple manufacturing and assembly, the main circuit can preferably be built from multiple PEBB’s (power electronic building blocks). Several different PEBB’s may be necessary to build a specific converter or one type may be sufficient in another case. Clearly, a low number of different building blocks required is best. A PEBB design may or may not simplify scalability of a concept. Ideally high voltage and higher power can be achieved by simply putting more PEBB’s in parallel and in series. Unfortunately, this is not possible with all topologies. The only truly modular and scalable topology in TABLE 17 is the M 2 LC. MC and SMC also provide nice modularity regarding switch arrangement; however, capacitor voltages and isolation requirements vary. Commutation is an important topic for all topologies. When scaling the concepts to higher voltages, insulation distances become larger and the capacitors have higher voltage rating. This introduces stray inductance in the commutation loops. The implementation becomes more difficult. Topologies using simple commutation loops and topologies using a small number of different commutation loops are therefore preferable, as each different loop needs to be designed carefully. In that respect, the M 2 LC performs best, as the individual cells can operate at relatively low voltage and all commutation loops are identical. Scalability is clearly best for this topology. The FC2 * x also applies all identical modules. The voltage can simply be scaled up by putting another row of modules on the DC link side. However, commutation with multiple modules becomes very challenging. All modules make use of the DC link directly, which leads to very large commutation loops when scaling the concept to higher number of levels. The commutation loops could remain constant if additional clamping capacitors are added at each module input. However, this leads to operational problems with potentially large ringing as many capacitors are dynamically connected in parallel. The balancing currents are only limited by stray inductances in this case. Therefore, the scalability is not very good. This is even more emphasized considering that the number of all components is rising with a square function of the number of levels. All MC based converters have good scalability but share the same problem of increasing capacitor voltages towards the supply side. The problem can be at least partially mitigated by splitting the DC link in two, resulting in the SMC and ANPC topologies. A PEBB based scaling is possible by may prove difficult in a practical implementation. The MLDC converter has differing commutation loops depending on the direction of the current. The number of components in the commutation loops is also proportionally increasing with the number of levels. Both properties are not desirable and make the implementation of the MLDC for high voltage and current challenging.
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
Page 6 and 7: iv Table of Contents 3.4 Generic ML
Page 8 and 9: vi Table of Contents 7.1 General mo
Page 10 and 11: viii Résumé français (French sum
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Page 22 and 23: Introduction 1 2 INTRODUCTION This
Page 24 and 25: Introduction 3 tighter capacitor di
Page 26 and 27: Introduction 5 TABLE 1, OPERATING R
Page 28 and 29: Introduction 7 2.3 Glossary Note th
Page 30 and 31: Introduction 9 2.4 Nomenclature Not
Page 32 and 33: Introduction 11 DPC DSP DTC FC FPGA
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86 3-L DC Link ML Converter Propert
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NP Control with Carrier based PWM 8
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Application and Verification 149 7
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Application and Verification 155 7.
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170 Conclusions and Outlook 8.1.2 M
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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