Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

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Application and Verification 151 TABLE 62, FEATURES OF THE DIFFERENT NP CONTROL SCHEMES (PART 1) CM / Impact on losses NP current range (I max – I min, measure for controlability) Harmonic performance in steady state (NP control not active) Output voltage distortion when NP control active DC link dimensioning (Note 1) Implementation, Computational effort at runtime Unconstrained DC CM injection, reference case no jumps / no impact on losses below standard range for reactive power operation (Note 2) According to base modulation scheme (e.g. PD PWM and /or CSVM) No increase compared to steady state standard value simple, low computational effort Real-time NP current function occasional jumps / small loss increase standard range According to base modulation scheme No increase compared to steady state Reactive power: smaller DC link possible simple, low computational effort 6 th harmonic no jumps / no impact on losses almost standard range including for reactive power operation According to base modulation scheme No increase compared to steady state Reactive power: smaller DC link possible simple, low computational effort Modified vectors jumps in each cycle / medium loss increase significantly above standard range at low modulation depth for all load angles According to base modulation scheme No increase compared to steady state Low modulation depth: smaller DC link possible off line calculation of suitable sequences, low computational effort (look up tables) Virtual vectors 1 jumps in each cycle / medium loss increase significantly above standard range at medium modulation depth for all load angles According to base modulation scheme No increase compared to steady state Reactive power: significantly smaller DC link off line calculation of suitable sequences, low computational effort (look up tables) Virtual vectors 2 jumps each cycle / large loss increase significantly above standard range at high modulation depth for all load angles According to base modulation scheme Significant increase of THD due to the 2 level steps Reactive power: significantly smaller DC link off line calculation of suitable sequences, low computational effort (look up tables) Note 1: The comments on DC link dimensioning only refer to the constraints imposed by NP controllability for a specific modulation scheme. In reality, other constraints may be dominant (e.g. energy for ride through). Note 2: standard range refers to the physical limitation of the NP current for a 3-L NPC in optimum modulation (without virtual vectors) as introduced in paragraph 4.7.1.2.
152 Application and Verification TABLE 63, FEATURES OF THE DIFFERENT NP CONTROL SCHEMES (PART 2) CM / Impact on losses NP current range (I max – I min, measure for controlability) Harmonic performance in stead state (NP control not active) Output voltage distortion when NP control active DC link dimensioning (Note 1) Implementation, computational effort at runtime Optimal sequence occasional jumps / medium loss increase above standard range for all load angles (Note 2) WTHD is slightly higher than for CSVM, but still better than many other modulation schemes No increase compared to steady state Depends highly on prediction horizon, theoretically smaller DC link possible Complex algorithms (prediction and optimization), high computational effort ANPC 3 smooth modulation, good switching loss distribution above standard range for all load angles According to base modulation scheme No increase compared to steady state Smaller DC link possible simple, low computational effort SMC A (Note 3) smooth modulation, good switching loss distribution above standard range for all load angles According to base modulation scheme No increase compared to steady state Smaller DC link possible simple, low computational effort SMC B (Note 3) Simultaneous commutations required, losses increase above standard range for all load angles According to base modulation scheme No increase compared to steady state Smaller DC link possible simple, low computational effort SMC FC (Note 3) Pure FC operation with doubled commutation voltage and increased losses NP current is zero Significantly increased distortion Significantly increased distortion Smaller DC link possible simple, low computational effort Note 1: The comments on DC link dimensioning only refer to the constraints imposed by NP controllability for a specific modulation scheme. In reality, other constraints may be dominant (e.g. energy for ride through). Note 2: standard range refers to the physical limitation of the NP current for a 3-L NPC in optimum modulation (without virtual vectors) as introduced in paragraph 4.7.1.2. Note 3: SMC A, SMC B, and SMC FC have distinctive properties. Best overall performance can be achieved if all three are combined within a given modulation scheme. (See also implementation of hysteresis modulator in chapter 1.)
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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x Résumé français (French summar
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xii Résumé français (French summ
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xiv Résumé français (French summ
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xvi Résumé français (French summ
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xviii Résumé français (French su
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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ML Converter Topologies 13 3 ML CON
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ML Converter Topologies 15 The four
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ML Converter Topologies 17 Each swi
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ML Converter Topologies 19 size doe
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ML Converter Topologies 21 plus (a)
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ML Converter Topologies 23 N >= 2,
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ML Converter Topologies 25 (a) (b)
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ML Converter Topologies 27 (a) (b)
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ML Converter Topologies 29 In a pra
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ML Converter Topologies 31 reality,
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ML Converter Topologies 33 All cons
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ML Converter Topologies 35 TABLE 16
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ML Converter Topologies 37 TABLE 17
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ML Converter Topologies 39 3.7.4.1
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ML Converter Topologies 41 f C sw =
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ML Converter Topologies 43 A second
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ML Converter Topologies 45 Limitati
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ML Converter Topologies 47 1 K M 2
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ML Converter Topologies 49 3.8 Exec
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52 3-L DC Link ML Converter Propert
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Page 191 and 192: 170 Conclusions and Outlook 8.1.2 M
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Page 216 and 217: Bibliography 195 10 BIBLIOGRAPHY [1
Page 218 and 219: Bibliography 197 [33] P. Steimer,
Page 220 and 221: Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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