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ML Converter Topologies 23 N >= 2, M >= 2 N M Generalized ML ANPC A higher number of output levels are available. The smallest step possible at the output is smaller than the lowest capacitor voltage. Such small steps can only be achieved by simultaneous commutations. Non optimum modulation schemes have to be used in the case of single commutations. 3.5.3 Modular multi level converter M 2 LC The M 2 LC [17] applies two converter branches per phase leg, one connecting to the positive supply and one connecting to the negative supply. Both branches are made of switched capacitors that can either be series connected or bypassed, thus generating a controllable DC voltage. Both branches can generate the same output voltages and are applied simultaneously. If full bridges instead of half bridges are used in the two branches, an AC input voltage can be applied. Direct ML AC/AC conversion based on such cascaded H-bridges has been proposed by Erickson [23], and by Glinka and Marquardt [24]. Different ways of implementing the individual branches are possible as shown in Figure 27. Graph (a) and (b) show two possible implementations with 2-L half bridges, the AC output of every half bridge connecting to either DC+ or DC- of an adjacent cell. Graph (b) shows one cell at the output shared by both branches, which reduces parts count, but increases the losses in this cell. Graph (c) connects outputs of adjacent cells and also makes direct series connection of two cell capacitors. This may have an impact on the design but is exactly equivalent from operational point of view. 2 1 (a) (b) (c) Figure 27, different implementations of the M 2 LC The M 2 LC capacitors can be operated in steady state by maintaining the same average current in all capacitors, independently of absolute current and output voltage. Consequently, all capacitors
24 ML Converter Topologies will charge and discharge simultaneously and the capacitor voltages stay balanced thanks to the symmetry of the AC output current. Additional control schemes are required to compensate for unbalance generated by any source of disturbance. Such schemes can be found in literature and are not subject of this thesis. Appendix 9.1 describes the steady state operation of the M 2 LC. Those calculations result in the following condition for the flying capacitor size (per module, assuming the worst case operating point of m = 0, ϕ = 0). C Iˆ 4ωUˆ out = (6) cap _ ac Equation (6) can be used directly for the dimensioning of the M 2 LC module capacitors (or flying capacitors) for a given maximum voltage ripple. 3.5.4 Other previously published topologies 3.5.4.1 Split DC link and FC based topologies FC (flying capacitor) cells can be combined in many more ways than indicated in the previous paragraphs. More input levels than three can be chosen and FC cells can be combined quite flexibly with half bridge switching cells. An overview and comparison of possible arrangements is given in [5]. This paper notably discusses the trade off between semiconductors and capacitors and compares the different topologies regarding parts count and total required energy in the flying capacitors. Examples of such converters are shown in Figure 28. A related approach is presented in [6], where a 7-L converter is proposed based on a 4-L DC link with a DC link selector stage and a SMC output stage (Figure 28 a). TABLE 7, NOMENCLATURE OF GENERAL SPLIT DC LINK CONVERTERS ACCORDING TO [5] x1y1[*z1] + x2y2[*z2] + x3y3[*z3] +… Topology name { FC , SC, FS SMC} x n ∈ , Types of converter stages from DC link to AC output FC SC FS Flying capacitor converter Semiconductor converter stage (half bridge form) Full semiconductor stage SMC Stacked multi cell stage { 1 N} y n ∈ : Number of cells in each converter stage { 1 ∞} z ∈ : Number of vertically stacked cells in each of the stages n
Page 1 and 2: THÈSE En vue de l'obtention du DOC
Page 3: Acknowledgements i ACKNOWLEDGEMENTS
Page 6 and 7: iv Table of Contents 3.4 Generic ML
Page 8 and 9: vi Table of Contents 7.1 General mo
Page 10 and 11: viii Résumé français (French sum
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Page 16 and 17: xiv Résumé français (French summ
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Page 22 and 23: Introduction 1 2 INTRODUCTION This
Page 24 and 25: Introduction 3 tighter capacitor di
Page 26 and 27: Introduction 5 TABLE 1, OPERATING R
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Page 32 and 33: Introduction 11 DPC DSP DTC FC FPGA
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NP Control with Carrier based PWM 8
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Application and Verification 149 7
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Application and Verification 155 7.
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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Christoph Haederli - Les thÃ¨ses en ligne de l'INP - Institut National ...

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