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3-L DC Link ML Converter Properties 63 1. Standard PD PWM or SVM with new CM injection concepts and subsequent state optimization for capacitor control for medium and high switching frequencies (chapter 4 and paragraph 6.1) 2. Optimal sequence SVM, with only 3 vectors to be applied per modulation period, applicable to low switching frequency applications (paragraph 6.2) 4.4.6 Modulator implementation and experimental verification Different modulator implementations have been used in the frame of this thesis. The modulator for the experimental verification of the SMC schemes (5.3.4) has been implemented totally on an FPGA with a generic PD PWM modulator and a subsequent state machine choosing the appropriate converter states (Figure 53). This modulator runs on a DSP based control system by LAPLACE [66]. The optimal sequence modulator introduced in 6.2 runs on an industrial control system (AC 800PEC by ABB). The code is implemented in MATLAB/Simulink. OPCoDe (Optimized Process of Code Development) generates the runtime code automatically from the Simulink and Matlab files. Figure 54, ABB’s AC 800PEC, core of the OPCoDe system A third separate modulator is running on the same OPCoDe system, is implemented also in Matlab but includes multiple modulators: all CB PWM schemes according to the paragraphs 5.1 and 5, as well as the SVM scheme with virtual vectors introduced in paragraph 6.1. These schemes are seamlessly integrated and can changeover from one to the other scheme in operation anytime. This feature is required by the hysteresis controller proposed in paragraph 7.3. The CB part of the modulator has asymmetric sampling, PD double edge modulation. Different PD PWM schemes (e.g. 3 rd harmonic injection or CSPD PWM) can be chosen. Switching times are pre-calculated (rather than determined by an actual reference carrier comparison) and communicated to the FPGA for gate signal generation. In this way, the gate signal generation on the FPGA can easily be shared with the SVM schemes, which are based on the NTV method. A calculation method with non perpendicular coordinates similar to [34], [67] or [68] is used for fast calculation. The same implementation of the modulator (same m-file) is used for simulation and experimental verification, which ensures good correspondence between simulation and real operation of the converter. A low power 5-L ANPC prototype (6kVA) has been used for all experimental verification regarding ANPC. The prototype has been specified for control investigations (rather than high power density) providing easy access to all relevant signals and flexible configuration of DC link and flying capacitors.
64 3-L DC Link ML Converter Properties Fiber optic control connections behind heat sinks Flying capacitors DC link capacitors IGBT’s Current sensors Power connections One PCB per phase Figure 55, 6kVA 5-L ANPC CH1 (dark blue): U out1 CH2 (red): CH3 (green): U out1 U NP CH4 (magenta): I out3 Math1 (red): U out1_2 Figure 56, 5-L ANPC waveforms at ϕ = 0.1, m = 0.9, PD PWM with 3 rd harmonic injection The optimum modulation waveform (only single level steps) with 5 levels in the phase voltage (red) and 9 levels in the phase to phase voltage (light blue) is nicely visible in Figure 56.
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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x Résumé français (French summar
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xii Résumé français (French summ
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xiv Résumé français (French summ
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xvi Résumé français (French summ
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xviii Résumé français (French su
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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Page 36 and 37: ML Converter Topologies 15 The four
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Page 46 and 47: ML Converter Topologies 25 (a) (b)
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Page 54 and 55: ML Converter Topologies 33 All cons
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Page 58 and 59: ML Converter Topologies 37 TABLE 17
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NP Control with Carrier based PWM 1
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NP Control with Optimal Sequence SV
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Application and Verification 149 7
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Application and Verification 151 TA
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Application and Verification 155 7.
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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