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NP Control with Carrier based PWM 113 TABLE 44, CELL STATUS SEQUENCE FOR STATE MACHINE BASED MODULATOR Cells status I NP I FC1 I FC2 I FC3 9 (1001) 1 0 + - 12 (1100) 1 0 0 0 6 (0110) 1 - 0 + 3 (0011) 1 0 0 0 5 (0101) 0 0 - - 12 (1100) 1 0 0 0 10 (1010) 0 + 0 + 3 (0011) 1 0 0 0 Average ¾ 0 0 0 Note that the choice of sequence has an impact on the capacitor dimensioning. The sequence {9-10-6-5} DSx applying type 3 NP states only applies two charging or discharging states for the flying capacitor number 3 in a row. The mixed long sequence {9-12-6-3-5-12-10-3} DSx alternates current signs in all flying capacitors, which allows for half the capacitor size for a given switching frequency. Carrier based modulation is possible also for the mixed sequences. However, the carriers for a specific cell are not purely triangular anymore. It is better to use generic carriers and then apply a state machine to determine the suitable cell states. A smooth transition from one modulation type to another is possible in this case. This approach with the generic carrier also allows using carriers in phase disposition (DP PWM with optimal harmonic performance). 1 α2 α3 α1 1 α2 α3 α1 1 α2 α3 α1 0 -1 0 1 s avg 0 -1 0 1 s avg 0 -1 0 1 s avg 1 I NP / I out 1 I NP / I out 1 I NP / I out 0 -1 0 1 s avg 0 -1 0 1 s avg 0 -1 0 1 s avg (a) standard NP states only (b) type 3 NP states only (c) mixed NP states {3,12} DSx {5,6,9,10} DSx {3,5,6,9,10,12} DSx Figure 72, NP current functions of the 5-L ANPC 3 with different modulation schemes 5.3.1.1.1 Commutation in ANPC type 3 ANPC type 1 and type 2 generate 2 level steps at the output when the stage without flying capacitors is operated. The ANPC type 3 on the other hand, all three stages can generate the minimum voltage step required for optimum modulation, which means all three stages can be operated simultaneously.
114 NP Control with Carrier based PWM 5.3.2 SMC modulation The following applies to the description of the subsequent modulation schemes: - Dedicated carriers are used for each switching cell. This does not yield lowest harmonics in 3 phase systems but is nice to illustrate the concept. Implementation can later be done with generic carriers to achieve PD PWM. - An index α L (0 to 1) is used for the output voltages from –U DC/2 to U DC/2, α 1 is the duty cycle of the upper cell, and α 2 is the duty cycle of the lower cell. - Ref is the reference (phase leg) duty cycle α L = 0.625 applied as an exemplary operating point. - The commutation cells are numbered according to Figure 73 C11 C12 C21 C22 Figure 73, 5-L SMC and cell numbering 5.3.2.1 Standard SMC modulation With the basic modulation scheme shown in Figure 74, only the upper FC converter of the SMC is modulated for output voltages above zero (α L>0.5). It can be seen that the switching cells C21 and C22 are not used for the output voltage chosen in the given example. The resulting average phase NP current is 75% of the phase output current. The flying capacitor is operated with an AC current with its fundamental at twice the carrier frequency. Figure 74, SMC standard modulation (α = 0.625)
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THÈSE En vue de l'obtention du DOC
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Acknowledgements i ACKNOWLEDGEMENTS
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iv Table of Contents 3.4 Generic ML
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vi Table of Contents 7.1 General mo
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viii Résumé français (French sum
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x Résumé français (French summar
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xii Résumé français (French summ
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xiv Résumé français (French summ
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xvi Résumé français (French summ
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xviii Résumé français (French su
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Introduction 1 2 INTRODUCTION This
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Introduction 3 tighter capacitor di
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Introduction 5 TABLE 1, OPERATING R
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Introduction 7 2.3 Glossary Note th
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Introduction 9 2.4 Nomenclature Not
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Introduction 11 DPC DSP DTC FC FPGA
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ML Converter Topologies 13 3 ML CON
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ML Converter Topologies 15 The four
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ML Converter Topologies 17 Each swi
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ML Converter Topologies 19 size doe
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ML Converter Topologies 21 plus (a)
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ML Converter Topologies 23 N >= 2,
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ML Converter Topologies 25 (a) (b)
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ML Converter Topologies 27 (a) (b)
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ML Converter Topologies 29 In a pra
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ML Converter Topologies 31 reality,
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ML Converter Topologies 33 All cons
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ML Converter Topologies 35 TABLE 16
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ML Converter Topologies 37 TABLE 17
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ML Converter Topologies 39 3.7.4.1
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ML Converter Topologies 41 f C sw =
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ML Converter Topologies 43 A second
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ML Converter Topologies 45 Limitati
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ML Converter Topologies 47 1 K M 2
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ML Converter Topologies 49 3.8 Exec
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52 3-L DC Link ML Converter Propert
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Application and Verification 163 7.
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Application and Verification 165 TA
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Application and Verification 167 7.
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170 Conclusions and Outlook 8.1.2 M
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172 Conclusions and Outlook 8.2 Out
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174 Conclusions and Outlook 8.3 Sum
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176 Appendix I = 1− ) (99) ( C 2
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178 Appendix TABLE 78, FLYING CAPAC
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180 Appendix 9.3 Single phase NP cu
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182 Appendix 9.4 States of the ANPC
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184 Appendix 9.5 NP currents as a f
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186 Appendix 9.5.3 Maximum and mini
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188 Appendix 9.6 NP current functio
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190 Appendix TABLE 91, NP CURRENT I
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192 Appendix TABLE 93, NP CURRENT I
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Bibliography 195 10 BIBLIOGRAPHY [1
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Bibliography 197 [33] P. Steimer,
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Bibliography 199 neutral point bala
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Bibliography 201 [88] J. Pou, J. Za
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