AMBA Design Kit Technical Reference Manual - ARM Information ...

List of FiguresFigure 3-19 Ahb2Ahb bridge ...................................................................................................... 3-48Figure 3-20 Ahb2AhbSyncDn bridge ......................................................................................... 3-48Figure 3-21 Ahb2AhbSyncUp bridge ......................................................................................... 3-49Figure 3-22 Ahb2AhbPass bridge .............................................................................................. 3-49Figure 3-23 Applications of synchronous AHB-AHB bridges ..................................................... 3-50Figure 3-24 System memory maps without address aliasing ..................................................... 3-51Figure 3-25 Address-aliasing hardware ..................................................................................... 3-52Figure 3-26 System memory maps with aliased addressing ...................................................... 3-52Figure 3-27 System memory maps with piecewise addressing ................................................. 3-53Figure 3-28 Bidirectional bridging .............................................................................................. 3-55Figure 3-29 Error cancel timing .................................................................................................. 3-56Figure 3-30 Error cancel using ErrorCanc timing ....................................................................... 3-56Figure 3-31 Asynchronous AHB-AHB bridge module components ............................................ 3-60Figure 3-32 AHB-Lite to AHB wrapper ....................................................................................... 3-65Figure 3-33 Interrupt controller components .............................................................................. 3-67Figure 3-34 ICPROTECTION Register bit assignments ............................................................ 3-74Figure 3-35 ICITCR Register bit assignments ........................................................................... 3-76Figure 3-36 ICITIP1 Register bit assignments ........................................................................... 3-77Figure 3-37 ICITOP1 Register bit assignments ......................................................................... 3-77Figure 3-38 ICPERIPHID0-3 Register bit assignments .............................................................. 3-79Figure 3-39 ICPCELLID0-3 Register bit assignments ................................................................ 3-81Figure 3-40 Downsizer module .................................................................................................. 3-85Figure 3-41 Funnel module ........................................................................................................ 3-93Figure 3-42 Typical funnel connection ....................................................................................... 3-93Figure 4-1 Remap and pause module components ................................................................... 4-2Figure 4-2 RPCPERIPHID0-3 Register bit assignment s ........................................................... 4-4Figure 4-3 RPCPCELLID0-3 Register bit assignments .............................................................. 4-6Figure 4-4 Example APB slave components .............................................................................. 4-9Figure 4-5 Peripheral to bridge multiplexor module components ............................................. 4-12Figure 4-6 Watchdog components ........................................................................................... 4-13Figure 4-7 WDOGCONTROL Register bit assignments .......................................................... 4-15Figure 4-8 WDOGRIS Register bit assignments ...................................................................... 4-16Figure 4-9 WDOGMIS Register bit assignments ..................................................................... 4-16Figure 4-10 WDOGLOCK Register bit assignments .................................................................. 4-17Figure 4-11 WDOGITCR Register bit assignments ................................................................... 4-18Figure 4-12 WDOGITOP Register bit assignments ................................................................... 4-18Figure 4-13 WDOGPERIPHID0-3 Register bit assignments ...................................................... 4-19Figure 4-14 WDOGPCELLID0-3 Register bit assignments ........................................................ 4-21Figure 4-15 Dual input timer components .................................................................................. 4-25Figure 4-16 Free-running timer block ......................................................................................... 4-26Figure 4-17 Prescale clock enable generation ........................................................................... 4-27Figure 4-18 TIMERXCONTROL Register bit assignments ........................................................ 4-30Figure 4-19 TIMERXRIS Register bit assignments .................................................................... 4-31Figure 4-20 TIMERXMIS Register bit assignments ................................................................... 4-32Figure 4-21 TIMERITCR Register bit assignments .................................................................... 4-33Figure 4-22 TIMERITOP Register bit assignments .................................................................... 4-33Figure 4-23 Peripheral identification register bit assignments ................................................... 4-34x Copyright © 2003, 2007 ARM Limited. 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