AMBA Design Kit Technical Reference Manual - ARM Information ...

Behavioral ModelsIf HREADY is asserted, the file reader proceeds to the second controlphase.Cycle 2The data read for the previous cycle is compared with the Data field afterapplying the mask and byte lane strobes. Any differences are reported tothe simulation environment. Unless the Burst field indicates a singletransfer, the file reader calculates the next address based on the Size andBurst values.Sequential commandThe sequential command S is a vector that provides data for a single beat within theburst. The file reader calculates the required address. A sequential command is validwhen a burst transfer is started by a read or write command.Figure 5-8 shows the sequential command timing diagram.Cycle n Cycle n+1CommandSSHADDRA(n)A(n+1)HTRANSSEQSEQHRDATAD(n)D(n+1)HWRITER/WHREADYFigure 5-8 Sequential command timingA sequential command is valid when a burst transfer has been started by a Read orWrite command:Cycle nThe file reader drives the calculated address, and HTRANS is SEQ toindicate the remaining transfers of the burst.If HREADY is asserted, the file reader proceeds to the second controlphase.Cycle n + 1 In a write burst, the file reader drives the Data field data and ignores theMask field.5-12 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C