AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsTable 3-13 Asynchronous AHB-AHB bridge interface signals (continued)SignalBlockClockdomainDirectionDescriptionHWDATAS[31:0]HWRITEMHWRITESSlaveinterfaceMasterinterfaceSlaveinterfaceSlave Input The 32-bit write data bus transfers data from the busmaster to the bridge during a write operation.Master Output When HIGH, this signal indicates a write transfer, andwhen LOW, a read transfer.Slave Input When HIGH, this signal indicates a write transfer, andwhen LOW, a read transfer.SCANENABLE Scan Slave Input Scan test mode enable.SCANINHCLKM Scan Master Input Scan chain input for HCLKM registers.SCANINHCLKS Scan Slave Input Scan chain input for HCLKS registers.SCANOUTHCLKM Scan Master Output Scan chain output for HCLKM registers.SCANOUTHCLKS Scan Slave Output Scan chain output for HCLKS registers.3-64 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C