AMBA Design Kit Technical Reference Manual - ARM Information ...

APB ComponentsTable 4-30 TIMERXCONTROL Register bit assignments (continued)Bits Name Function[3:2] TimerPre Prescale bits:00 = 0 stages of prescale, clock is divided by 1, default01 = 4 stages of prescale, clock is divided by 1610 = 8 stages of prescale, clock is divided by 25611 = Undefined, do not use.[1] Timer Size Selects 16/32 bit counter operation:0 = 16-bit counter, default1 = 32-bit counter.[0] One Shot Count Selects one-shot or wrapping counter mode:0 = wrapping mode, default1 = one-shot mode.Interrupt Clear RegisterAny write to the TIMERXINTCLR Register clears the interrupt output from thecounter.Raw Interrupt Status RegisterThis register is read-only. It indicates the raw interrupt status from the counter. Thisvalue is ANDed with the timer interrupt enable bit from the Timer Control Register tocreate the masked interrupt, that is passed to the interrupt output pin. Figure 4-19 showsthe register bit assignments.31 1 0UndefinedRaw Timer InterruptFigure 4-19 TIMERXRIS Register bit assignmentsARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 4-31