AMBA Design Kit Technical Reference Manual - ARM Information ...

APB ComponentsTimerclockenableControlDivideby 16Divideby 16Prescale selectTimer clockenable afterprescalingFigure 4-17 Prescale clock enable generationNoteThis selection is in addition to any similar facility already provided as part of any clockgeneration logic external to the Timers.Interrupt generationAn interrupt is generated when the full 32-bit counter reaches zero, and is only clearedwhen the TimerXClear location is written to. A register holds the value until theinterrupt is cleared. The most significant carry bit of the counter detects the counterreaching zero.You can mask interrupts by writing 0 to the Interrupt Enable bit in the Control register.Both the raw interrupt status, prior to masking, and the final interrupt status, aftermasking, can be read from status registers.The interrupts from the individual counters, after masking, are logically ORed into acombined interrupt, TIMINTC, provides an additional output from the Timerperipheral.4.5.3 ClockingThe timers have two clock inputs, PCLK and TIMCLK. PCLK is the main APBsystem clock, and is used by the register interface. TIMCLK is the input to the prescaleunits and the decrementing counters. A pulse on TIMCLK must be qualified by theappropriate TIMCLKENx being HIGH.The design of the timers assumes that PCLK and TIMCLK are synchronous. To enablethe counter to operate from a lower effective frequency than that at which PCLK isrunning, you can do either of the following:• both PCLK and TIMCLK inputs are connected to the APB PCLK signal, andTIMCLKENx is pulsed HIGH at the required frequency, synchronized to PCLKARM DDI 0243C Copyright © 2003, 2007 ARM Limited. All rights reserved. 4-27