AMBA Design Kit Technical Reference Manual - ARM Information ...

AHB ComponentsAhb2Ahb (1:1)This is a fully registered bridge for connecting AHB buses that share a common clock.This bridge includes one level of write buffering to enable zero wait-state write transfersacross it. Figure 3-19 shows the Ahb2Ahb bridge.Ahb2AhbAHB1(HCLK)SlaveAhb2LiteMasterErrorCancHCLKIncroverrideHCLKLite2AhbAHB2(HCLK)HCLKAHB-LiteHCLKFigure 3-19 Ahb2Ahb bridgeAhb2AhbSyncDn (N:1)This bridge connects buses running at different, synchronous frequencies, where clocksshare concurrent edges, and where the master is clocked at the same or a higherfrequency than the slave.Figure 3-20 shows the Ahb2AhbSyncDn bridge.Figure 3-20 Ahb2AhbSyncDn bridgeAhb2AhbSyncUp (1:N)This bridge connects buses running at different, synchronous frequencies, where clocksshare concurrent edges, and where the master is clocked at the same or a lowerfrequency than the slave. Figure 3-21 on page 3-49 shows the Ahb2AhbSyncUp bridge.3-48 Copyright © 2003, 2007 ARM Limited. All rights reserved. ARM DDI 0243C